Debugging at the Electronic System Level

Refinement rules for the automatic TLM-to-RTL conversion of temporal assertions

“…In that context, SystemC TLM (Transaction-Level Modeling) [1], [2] has gained acceptance, as it favors architecture exploration and early software development while improving simulation performance [3]. As shown on Figure 1, the SoC design flow [4], [5] usually starts from the system specification. From this specification, the global SoC architecture is defined by system architects, and a virtual prototype of the hardware platform can be developed as soon as the functional specification of the IP blocks is available.…”

A tool for the automatic TLM-to-RTL conversion of embedded systems requirements for a seamless verification flow

“…The ESL flow complies with the need for hardware/software co-design and early functional verification. Figure 1 shows a typical ESL design flow as described by [2], [3]. Starting with a textual specification, the first step consists in obtaining a specification of the entire system capturing the basic functionalities and requirements regardless of architectural and timing concerns.…”

“…The resulting implementation has to be verified with respect to the golden model. [2] There are increasing demands for effective verification flows that can help to reduce the verification cost. For example, [4] reports a recent study on the total percentage of project time spent in verification: Figure 2 shows that in 2007, the average (mean) project time spent in verification was 49 percent, while it increased to 56 percent in 2010 and 2012.…”