Debugging sequential circuits using Boolean satisfiability

Abstract

Logic debugging of today's complex sequential circuits is an important problem. In this paper, a logic debugging methodology for multiple errors in sequential circuits with no state equivalence is developed. The proposed approach reduces the problem of debugging to an instance of Boolean Satisfiability. This formulation takes advantage of modern Boolean Satisfiability solvers that handle large circuits in a computationally efficient manner. An extensive suite of experiments with large sequential circuits confirm the robustness and efficiency of the proposed approach. The results further suggest that Boolean Satisfiability provides an effective platform for sequential logic debugging.