Debugging Support for Pattern-Matching Languages and Accelerators

Abstract

Programs written for hardware accelerators can often be difficult to debug. Without adequate tool support, program maintenance tasks such as fault localization and debugging can be particularly challenging. In this work, we focus on supporting hardware that is specialized for finite automata processing, a computational paradigm that has accelerated pattern-matching applications across a diverse set of problem domains. While commodity hardware enables highthroughput data analysis, direct interactive debugging (e.g., single-stepping) is not currently supported. We propose a debugging approach for existing commodity hardware that supports step-through debugging and variable inspection of user-written automata processing programs. We focus on programs written in RAPID, a domain-specific language for pattern-matching applications. We develop a prototype of our approach for both Xilinx FPGAs and Micron's Automata Processor that supports simultaneous highspeed processing of data and interactive debugging without requiring modifications to the underlying hardware. Our empirical evaluation demonstrates low clock overheads for our approach across thirteen applications in the ANMLZoo automata processing benchmark suite on FPGAs. Additionally, we evaluate our technique through a human study involving over 60 participants and 20 buggy segments of code. Our generated debugging information increases fault localization

FlexAmata: A Universal and Efficient Adaption of Applications to Spatial Automata Processing Accelerators

“…Performance results for FPGA-based implementations are presented in Table 4. A modified REAPR is presented in [13] on thirteen benchmarks from ANMLZoo. We compared our results to this implementation from the published results and, thus, limit Table 4 to these thirteen benchmarks.…”

An Overlay Architecture for Pattern Matching

“…we assume total number of STEs (overlay size) is 16. The size of the output region is 8, so the number of groups is 2 (= 16 8 ). We instance that the number of priority encoders in each group is 4.…”

“…Datasets comprised of symbolic data, such as genomic sequences, item sets, graph edges, web data, biological data, and data packets, are growing rapidly in size and computational requirements. Computing such data often involves pattern matching based computation, for example when discovering motifs [29], de novo assembling [25], web-search and ranking [6] , question answering systems [24] [10], compression in NoSQL systems [26] [20], approximate string matching [16], calculating the edit distance between two genomic sequences [34], signature-based threat detection [8], association rule mining [15], and data-packet inspection [8]. Such pattern matching computations are algorithmically reducible to the simulation of either Determinitic and Non-deterministic Finite Automata (DFA and NFA).…”

PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development

“…At the twilight of Moore's Law, reconfigurable-based accelerators have emerged capable of delivering energy, cost, and performance benefits compared with CPU and ASICs platforms [1,10,15,19,20,24,51,58,63]. The boom of data-center-based FPGA deployments [17,45,67] further provides more opportunities to diverse FPGA-based applications on image processing [12,31], machine learning [13,19], and data analysis [8,13]. Xilinx now provides Alveo Data-center cards that communicate with a Linux host via PCIe similar to GPUs.…”