Decimal to Excess-3 and Excess-3 to Decimal Code Converters in QCA Nanotechnology

Abstract

Nowadays Quantum-dot Cellular Automata (QCA) is one of the new technologies in nanoscale which can be used in future circuits. Most digital circuits are implemented with CMOS technology, but CMOS has some problems like power consumption and circuit size. So, for solving these problems a new method (QCA) is presented. It is clear that converters play a crucial role in the digital world. So, due to the aforementioned point, in this paper, two digital code converters, containing an excess-3 to decimal, and a decimal to excess-3 code converter are presented. The tile method is used to design proposed circuits in quantum-dot cellular automata (QCA) nanotechnology. The tile method gives a unique block for the majority and NOT gates. This property facilitates integration. Both of the proposed code converters have 1.75 clock cycles delay and have an energy dissipation of about 100meV. In the excess-3 code to decimal converter, 516 cells are used, which occupy an area equal to 0.43µm 2 also in the decimal to excess-3 code converter. 321 cells are used, which occupy an area equal to 0.28 µm 2 .

Design and Performance Analysis of 6H-SiC Metal-Semiconductor Field-Effect Transistor with Undoped and Recessed Area under Gate in 10nm Technology

“…The recessed gate design further enhances the reduction of short-channel effects by allowing better control over the gate-tochannel distance. Short-channel effects, such as draininduced barrier lowering (DIBL) and subthreshold slope degradation, are minimized, leading to improved device performance for short-channel lengths [28]. The reduced lateral electric field in combination with precise gate control results in better subthreshold characteristics and improved transistor behavior.…”

Design and Analysis of Hetero Dielectric Dual Material Gate Underlap Spacer Tunnel Field Effect Transistor

“…These findings revealed that the ON drain current increases linearly as temperature rises, whereas the drain OFF current rises exponentially as temperature rises. The primary electrical factors that govern the transistor's properties in analogue or digital circuits, such as ION /IOFF ratio, drain induced barrier lowering (DIBL), and VT, are all affected by the transistor's working temperature dependent characteristics as shown in Figure 11 [32].…”