Decision Feedback Equalizer Architectures With Multiple Continuous-Time Infinite Impulse Response Filters

Shahramian, Shahriar; Yasotharan, Hemesh; Carusone, Anthony Chan

doi:10.1109/tcsii.2012.2195055

Cited by 23 publications

(4 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Note that the falling edges of the clock are the zero-crossing points of the data. Therefore, the defined JI includes only the deterministic jitter caused by the residual ISI or ringing in the time domain [18]. The sum of ISI and JI samples is less than 6.5% of the main cursor sample which implies that the eye has a wide internal opening area, as evident also from the eye diagram in Figure 9a, obtained through simulation.…”

Section: Bandwidth Extension and Signal Integritymentioning

confidence: 90%

A Novel Inductorless Design Technique for Linear Equalization in Optical Receivers

Abdelrahman

Williams

Liboiron-Ladouceur

et al. 2022

JLPEA

View full text Add to dashboard Cite

To mitigate the trade-off between gain and bandwidth of CMOS multistage amplifiers, a receiver front-end (FE) that employs a high-gain narrowband transimpedance amplifier (TIA) followed by an equalizing main amplifier (EMA) is proposed. The EMA provides a high-frequency peaking to extend the FE’s bandwidth from 25% to 60% of the targeted data rate (fbit). The peaking is realized by adding a pole in the feedback paths of an active feedback-based wideband amplifier. By embedding the peaking in the main amplifier (MA), the front-end meets the sensitivity and gain of conventional equalizer-based receivers with better energy efficiency by eliminating the equalizer stages. Simulated in TSMC 65 nm CMOS technology, the proposed front-end achieves 7.4 dB and 6 dB higher gain at 10 Gb/s and 20 Gb/s, respectively, compared to a conventional front-end that is designed for equal bandwidth and dissipates the same power. The higher gain demonstrates the capability of the proposed technique in breaking the gain-bandwidth trade-off. The higher gain also reduces the power penalty incurred by the decision circuit and improves the sensitivity by 1.5 dB and 2.24 dB at 10 Gb/s and 20 Gb/s, respectively. Simulations also confirm that the proposed FE exhibits a robust performance against process and temperature variations and can support large input currents.

show abstract

Section: Bandwidth Extension and Signal Integritymentioning

confidence: 90%

A Novel Inductorless Design Technique for Linear Equalization in Optical Receivers

Abdelrahman

Williams

Liboiron-Ladouceur

et al. 2022

JLPEA

View full text Add to dashboard Cite

show abstract

“…The slicer based on Strong-Arm structure is mainly used to quantize the input signal, which works as 1-bit ADC [30]. The appropriate number of DFE taps can be determined according to the relationship between the number of taps and eye opening [31,32,33]. Fig.…”

Section: -Tap Half Rate Dfe With Speculative Tapmentioning

confidence: 99%

A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology

Zhu

Chu

2023

IEICE Electron. Express

View full text Add to dashboard Cite

This work proposes a RX front-end structure, which is used for channel equalization of 25 Gb/s high-speed links. This design includes two parts, linear equalizer and decision feedback equalizer. Linear equalizer consists of the variable gain amplifier, the continuous-time linear equalizer and the output buffer, which provide 19 dB peaking gain around the Nyquist frequency. The half-rate decision feedback equalizer with one speculative tap is cascaded after the buffer to eliminate residual inter-symbol interference. The circuit layout occupies an area of 0.005 mm 2 designed in 65 nm CMOS, the power consumption of which is 96 mW under 1.2 V power supply. The design is used to equalize the FR-4 backplane channel, of which the insertion loss reaches 35 dB at 12.5 GHz. The result shows that both the voltage margin and time margin of the receiver signal reach 171 mV and 0.61 UI at the BER of 10 −12 , respectively.

show abstract

“…1(b) also consumes a lot of power as the number of taps increases to remove ISI [4,17]. So, infinite impulse response (IIR) DFE has been reported to mitigate power penalty [18,19,20,21,22]. The IIR filter replaces the multiple discrete taps to reduce active area and power consumption.…”

Section: Introductionmentioning

confidence: 99%

A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process

Kang

Song

2021

IEICE Electron. Express

View full text Add to dashboard Cite

This paper describes quad-rate 1-FIR 2-IIR decision feedback equalizer (DFE) with summer reduction technique for high-speed serial communication in a 65nm CMOS technology. The proposed DFE halves the number of summers by using resettable slicer and summer with multiplexer. Therefore, the proposed DFE reduces power consumption significantly because summer dissipates a lot of power. The DFE that is verified by pre-layout simulations achieved 0.69 unitinterval (UI) eye-opening. The proposed DFE that is designed with a 65-nm technology operates at 28Gb/s and occupies 0.023mm 2 . Finally, the power efficiency of the proposed DFE is 0.88-pJ/bit.

show abstract

Decision Feedback Equalizer Architectures With Multiple Continuous-Time Infinite Impulse Response Filters

Cited by 23 publications

References 9 publications

A Novel Inductorless Design Technique for Linear Equalization in Optical Receivers

A Novel Inductorless Design Technique for Linear Equalization in Optical Receivers

A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology

A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process

Contact Info

Product

Resources

About