DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors

Abstract

Increases in peak current draw and reductions in the operating voltage of processors stress the importance of dealing with voltage fluctuations in processors. Noise-margin violations lead to undesired effects, like timing violations, which may result in incorrect execution of applications. Several recent architectural solutions for inductive noise have been proposed that, unfortunately, have a strong correlation to the underlying power-delivery package model and require a feedback loop that is largely constrained by the voltage/current sensor characteristics. The resulting solutions are not robust across a wide range of microprocessor designs and packaging technologies. This paper proposes a DelayedCommit and Rollback scheme (DeCoR) that guarantees correctness, insensitive to the package model or the responsiveness of the voltage sensors. In particular, our approach recovers from, rather than attempting to avoid, voltage emergencies. This approach incurs a small performance penalty when compared to an ideal machine that does not have voltage emergencies. We show that explicit checkpoint-recovery schemes, intended to handle infrequent events, e.g., radiation-induced soft errors, suffer from large performance overheads for frequently-occurring voltage emergencies. DeCoR requires very few modifications to modern processor designs, as it leverages the existing store queue and reorder buffers. Unlike conventional designs that conservatively protect all components of the processor from inductive noise with overly-large timing margins, our approach only requires conservative protection of the architected register state and cache write paths.

iGPU: Exception support and speculative execution on GPUs

“…It allows for coarser and simpler detection mechanisms, but requires more sophisticated recovery support due to longer detection latencies. We base the remainder of our discussion on a previous proposal by Gupta et al for CPUs [17]. They divide processors into rollback protected and timing-margin protected regions, using both a re-order buffer and store queue to recover from voltage mis-speculation only in the rollback protected regions (pipeline regions).…”

“…In traditional CPUs, speculation recovery support is used for multiple purposes ranging from out-of-order execution [38] and branch prediction [42], to hardware fault recovery [30] and circuit-level speculation [17]. However, modern GPUs implement simple, in-order cores to maximize throughput, and hence have little or no hardware support for speculative execution.…”

“…As a concrete example, this section focuses specifically on the iGPU mechanisms to support speculative circuitlevel techniques, which have received much attention in recent years [3,8,12,16,17,31]. These circuit-level techniques speculatively assume common-case timing and voltage conditions, with occasional recovery employed under worst-case conditions.…”

“…However, we argue that even with a 1 The compiler region formation is an IR-level analysis that does not directly modify generated device code and hence incurs no overhead. DeCoR [17] 1% 10% Emergency Prediction [31] 0.01% 10% Razor [12] 1% 15% Razor II [8] 0.1% 15% Table 2: Circuit speculation techniques and their corresponding error rate and V dd reduction (approximate).…”

“…Shortly after the development of exception support in CPUs, speculation was developed as a mechanism to transparently handle "difficult" code, and a recent study claims that GPUs must similarly begin incorporating techniques like speculation to expand the domains they can target [6]. Speculation support has also increasingly been proposed for handling recovery from hardware reliability problems in CPUs [4,17,30]. Such problems, which include variability, noise, and excessive guard-banding, are also emerging problems for GPUs [7].…”