Decoupled victim model for the analysis of crosstalk noise between on-chip coupled interconnects

Abstract

Crosstalk noise due to parasitic couplings between two closely located neighboring wires has significant impact on the performance of the high speed DSM chips. Analysis of crosstalk effect using a single wire with all of its coupling parameters is much easier and very convenient for determining the maximum effect of the crosstalk noise both in terms of glitch and delay. With this objective, in this paper a decoupled and distributed RLGC transient model of the victim wire is introduced which takes into account all coupling effects and is very fast, highly flexible and yet accurate enough. Using this decoupled victim model also some analytical or numerical approaches for determining the critical values of influencing parameters can be developed. The efficacy of the decoupled victim model is also compared with the coupled two interconnects' PSPICE and MATLAB simulation results, which show comparable performance for the model's accuracy but significantly superior performance for simulation speed.

An ABCD parameter-based modeling and analysis of crosstalk induced effects in single-walled carbon nanotube bundle interconnects

“…Then by inverse laplace transform, we can find out the response in time domain. A number of works use this method [13], [25]- [26]. It is also impractical to use SPICE simulation methods for large VLSI chips as it would lead to significant delay in the design cycle.…”

“…By solving (20), the final output voltages 1(s), 2(s) and 3(s) can be represented in terms of the inputs 1(s), 2(s) and 3(s) in matrix form as shown in (25). The exact expressions of 1(s), 2(s) and 3(s) in (25) are shown in (26), (27) and (28) Table(III).…”

“…Here, The transfer function for the crosstalk delay or noise evaluation in the victim net will be denoted as H(s) throughout the paper. H(s) can be derived from(25) and the representation of it for different evaluation conditions (i.e., crosstalk delay and noise) is shown in…”

Application of Evolutionary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems

“…8.2a, the victim line has a falling transition and a rising transition is applied at the aggressor and therefore, signal delay increases thus decreasing the circuit speed. Several physical design (Vittal and Marek-Sadowska 1997;Elgamel et al 2005;Hunagund and Kalpana 2010) and analysis tools (Agarwal et al 2006;Kaushik and Sarkar 2008;Palit et al 2009;Shahin and Pedram 2008) are being developed to aid in designs that minimize cross talk. 8.2b, if the transitions are in the same direction, delay of the signal decreases thus increasing circuit speed.…”