Deep Level Assessment of n-Type Si/SiO₂Metal-Oxide-Semiconductor Capacitors with Embedded Ge Quantum Dots

Abstract

This paper reports on a Deep-Level Transient Spectroscopy (DLTS) study of n-type silicon Metal-Oxide-Semiconductor capacitors with Ge Quantum Dots (QDs) embedded in a SiO 2 gate dielectric. For a zero-dot reference and in capacitors fabricated with a 1, 2 or 3 nm amorphous Ge layer similar spectra have been obtained. They are characterized by a peak at or above room temperature for a bias pulse in depletion and by an electron trap around 200 K, which is shown to be associated with dangling bond acceptor states at the Si/SiO 2 interface. The maximum density of states increases with average Ge QD size, while the average activation energy, corresponding with the peak maximum position shifts to lower values. Although no direct evidence of electron tunneling to the Ge QDs has been found so far, there is a marked impact of their presence on the Capacitance-Voltage characteristics, resulting in an increase in the accumulation capacitance with QD size, a shift of the flatband voltage toward more positive gate bias and a counterclockwise hysteresis, associated with the charging and discharging of QD levels and related Ge traps in the SiO 2 .

Deep levels in metal–oxide–semiconductor capacitors fabricated on n-type In0.53Ga0.47As lattice matched to InP substrates

“…However, what certainly must be considered in the present experiments is the occurrence of the minority carrier response in a MOScap, during the relaxation of the capacitance after the bias pulse from deep depletion into accumulation [50][51][52][53]. Minority carriers (holes) generated during the transient period will be attracted by the negative gate bias, building up an inversion layer at the In 0.53 Ga 0.47 As/Al 2 O 3 interface.…”