Deep-Level Transient Spectroscopy of MOS Capacitors on GeSn Epitaxial Layers

Abstract

Deep levels present in MOS capacitors, fabricated on GeSn epitaxial layers on Ge-on-Si substrates have been studied by Deep-Level Transient Spectroscopy (DLTS). The gate dielectric is composed of 9 nm Al2O3 deposited by Molecular Beam Epitaxy (MBE) on two different types of Interfacial Oxide Layers (IOL). It is shown that the density of interface traps (Dit) near the valence band edge is significantly reduced for GeSn epilayers compared with the same gate stack on a Ge cap. At the same time, several deep-level traps in the germanium depletion region have been observed, whereof the origin is discussed.

Review—Device Assessment of Electrically Active Defects in High-Mobility Materials

“…106 In the case of relaxed Ge virtual substrates, DLTS revealed the presence of a band of hole traps close to mid gap in p-type layers, with a peak maximum at about E V +0.28 eV. 105,107 Other studies reported shallower hole traps and a near mid-gap electron trap. 108 It has also been shown that the presence of TDs in SRBs accelerates the diffusion of n-type dopants (e.g., P) and, therefore, affects the (shallow) junction formation.…”

Identification of Deep Levels Associated with Extended and Point Defects in GeSn Epitaxial Layers Using DLTs

“…Transmission Electron Microscopy (TEM) analysis of the structures has shown pin holes in the Al 2 O 3 oxide layers. Consequently in figure 1b, we observe a high depletion current, indicating that the devices are quite leaky, for the relatively large area under investigation (21). The pin holes as well facilitates minority electron injection from the gate during forward bias for carrier recombination.…”

“…For that purpose MOS capacitors with a 9nm Al 2 O 3 gate dielectric on top of a GeO 2 interface layer have been fabricated. Initial DLTS results have been reported previously (21). Here a more detailed study of the deep levels is undertaken to identify their origin.…”

“…The TDs and bulk crystal defects are known to introduce defect levels in the band gap of the semiconductors, which can act as traps or generation/recombination centers, which affect the mobility and noise properties of the semiconductor (19,20), prominently leading to enhanced leakage current. Another important issue to be addressed is the interface quality between the semiconductor and high-k dielectric, which influences the surface potential, charge transport and frequency response of the devices (21). Therefore, it is viable to say that the key to success of compound CMOS device technology lies in the control and understanding of the defects, in both the active region and the oxide-semiconductor interface.…”

(Invited) On the Electrical Activity of Extended Defects in High-Mobility Channel Materials

“…In order to have a more detailed understanding of origin of the electrical activity of TDs in (Si)Ge hetero-epitaxial layers, more fundamental analysis methods can be applied to p-n junctions, like Deep Level Transient Spectroscopy (DLTS) [20]. In the case of relaxed Ge virtual substrates, DLTS has revealed the presence of a band of hole traps close to mid gap in p-type layers, with a peak maximum at about E V +0.28 eV [19,21]. Other studies reported shallower hole traps and a near mid-gap electron trap [22].…”