Deep submicron microprocessor design issues

Optimizing pipelines for power and performance

“…As derived by Dubey and Flynn in [7], and Larson and Davidson (cited in Chapter 2 of [14]), the throughput of the above machine in the absence of stalls is given by G = (…”

“…These chips are still somewhat below the power and power density limits afforded by the package/cooling solution of choice in server markets targeted by such processors. In designing future processors, however, energy efficiency is known to have become one of the primary design constraints [7,1].…”

Towards adaptive balanced computing (ABC) using reconfigurable functional caches (RFCs)

“…There are several challenges in the design of next generation microprocessors, such as instruction-level parallelism, compiler optimizations, higher reliability, adaptability, and mem ory capacity/performance [14] with a billion transistors [15,16]. To overcome the gap between processor and memory technology, the size of on-chip cache memory has been constantly in creasing.…”

“…In deep-submicron technology, we can have billions of transistors running at gigahertz frequencies [14,15,16]. This trend promises a lot of challenges and possibilities in micro processor architecture and design.…”

Why Area Might Reduce Power in Nanoscale CMOS

“…If we fix VTH, then as Flynn et al [13] point out, F ∝ V . The assumption of constant load capacitance is valid for organizations such as asynchronous spatial architectures that exhibit small Rent exponents for which the fanout and interconnect length do not depend greatly on the size of the circuit [14].…”