Deep-trap SILC (stress induced leakage current) model for nominal and weak oxides

Kamohara, S.; Park, D.; Hu, Chenming

doi:10.1109/relphy.1998.670443

Cited by 30 publications

(19 citation statements)

References 8 publications

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“…Considering the different slope changes between 5. Schematic for two different inelastic tunneling modes through defects inside the TO (modified from [9]). Process (a) includes FN tunneling, which will have Φ dependence.…”

Section: Resultsmentioning

confidence: 99%

Comprehensive Understanding on the Role of Tunnel Oxide Top Nitridation for the Reliability of Nanoscale Flash Memory

Kim

Sarpatwari

Koka

et al. 2013

IEEE Electron Device Lett.

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We report the role of tunnel oxide (TO) top nitridation (TN) in the reliability of nanoscale Flash memory and provide comprehensive understanding for the mechanism. TN was expected to potentially improve the TO quality by protecting against damages from edge encroachment and other processes. However, instead of net improvement, we found a tradeoff between endurance (charge trap) and retention (charge detrap and leakage) in the reliability of the cell array. We find that more charges are trapped in the TO with increasing nitrogen concentration, although detrapping can be decreased in a limited concentration. This suggests that the defect in the TN layer (SiON) includes a deep energy trap, thus resulting in a more strongly bound charge. Increasing nitrogen concentration also degrades charge retention from TO leakage but can be better for the same electrical oxide thickness. Evaluating a band diagram suggests that the possible improvement arises from the greater physical oxide thickness, although the barrier height for electron transmission is lower. This suggests that TO leakage is dominated by an inelastic trap-assisted tunneling mode using multiple direct tunneling through deep oxide traps. The results are indicative of the intrinsic impact of TN, regardless of bulk nitrogen or hydrogen incorporation.

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Section: Resultsmentioning

confidence: 99%

Comprehensive Understanding on the Role of Tunnel Oxide Top Nitridation for the Reliability of Nanoscale Flash Memory

Kim

Sarpatwari

Koka

et al. 2013

IEEE Electron Device Lett.

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“…Regime A (HfO layer) shows a clear increment in current, which can be associated to generation of defects in this layer, leading to SILC. Actually, the data has been correctly fitted to a SILC model [10], which attributes this current to one trap assisted tunneling. The fitting points out that the traps are close to the HfO SiO interface.…”

Section: Resultsmentioning

confidence: 99%

Charge trapping and degradation of HfO/sub 2//SiO/sub 2/ MOS gate stacks observed with enhanced CAFM

Aguilera

Porti

Nafría

et al. 2006

IEEE Electron Device Lett.

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In this letter, a prototype of conductive atomic force microscope with enhanced electrical performance has been used to separately investigate the effect of the electrical stress on the SiO 2 and the HfO 2 layers of a high-gate stack. Charge trapping in HfO 2 native defects and degradation of both layers have been observed, depending on the stress level.Index Terms-Atomic force microscopy (AFM), dielectric breakdown, HfO 2 , high-dielectric, MOS device.

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“…Therefore, absolute values cannot be considered in analyzing the electrical conduction and only relative variations will be taken into account in investigating the role of the Si-nc. A fit of the low field I-V curve to the model proposed by Kamohara et al, 26 which estimates the stress induced leakage current that flows through MOS structures with traps generated during the electrical stress, shows that these defects are located near the tip-sample interface. 4͒, for the case of reference samples ͑inset of Fig.…”

Section: B Conduction Mechanismsmentioning

confidence: 96%

Nanoscale electrical characterization of Si-nc based memory metal-oxide-semiconductor devices

Porti

Avidano

Nafrı́a

et al. 2007

Journal of Applied Physics

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Conduction mechanisms and charge storage in Si-nanocrystals metal-oxide-semiconductor memory devices studied with conducting atomic force microscopy J. Appl. Phys. 98, 056101 (2005); 10.1063/1.2010626The effect of additional oxidation on the memory characteristics of metal-oxide-semiconductor capacitors with Si nanocrystals Appl. Phys. Lett. 82, 4818 (2003); 10.1063/1.1587273 Nanocrystal metal-oxide-semiconductor memories obtained by chemical vapor deposition of Si nanocrystals Memory effects related to deep levels in metal-oxide-semiconductor structure with nanocrystalline SiIn this work, standard and nanoscale experiments have been combined to investigate the electrical properties of metal-oxide-semiconductor ͑MOS͒ memory devices with silicon nanocrystals ͑Si-nc͒ embedded in the gate oxide. The nanometer scale analysis has been performed with a conductive atomic force microscope ͑C-AFM͒ which, thanks to its high lateral resolution, allows the study of areas of only few hundreds of nm 2 . Therefore, with this technique, a very reduced number of Si-nc can be investigated. We have studied the conduction mechanisms, the retention time, and the amount of charge stored in the Si-nc of these structures. The results have demonstrated that Si-nc enhance the gate oxide electrical conduction due to trap assisted tunneling. On the other hand, Si-nc can act as trapping sites. The amount of charge stored in Si-nc has been estimated through the change induced in the barrier height measured from the current-voltage ͑I-V͒ curves ͑at the nanoscale, with C-AFM͒ and from the flat band voltage shift determined from the capacitance-voltage ͑C-V͒ characteristics measured on polygated structures. Both procedures have shown an occupation level of ϳ20% of the Si-nc. The retention times, estimated at the nanoscale and from standard electrical characterization, are consistent. Moreover, contrary to standard characterization techniques, C-AFM allows the mesurement of lateral leakage currents in memories based on high density trapping sites. All these results allow one to conclude that C-AFM is a very suitable tool in performing a detailed investigation of the performance of memory devices based on MOS structures with Si-nc at the nanoscale.

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Deep-trap SILC (stress induced leakage current) model for nominal and weak oxides

Cited by 30 publications

References 8 publications

Comprehensive Understanding on the Role of Tunnel Oxide Top Nitridation for the Reliability of Nanoscale Flash Memory

Comprehensive Understanding on the Role of Tunnel Oxide Top Nitridation for the Reliability of Nanoscale Flash Memory

Charge trapping and degradation of HfO/sub 2//SiO/sub 2/ MOS gate stacks observed with enhanced CAFM

Nanoscale electrical characterization of Si-nc based memory metal-oxide-semiconductor devices

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