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A novel Shallow Trench Isolation(ST1) technology has been proposed for the device fabrication using SO1 wafers. The trench sidewall osiclation is replaced with MTO(Medium Temperature Oxide) and Silicon Nitridc(SiN) to prevent the SO1 bending problem. SIN Liner over MTO scheme showed the additional benefits such as reduced field oside recess and improvcd gate oxide quality. Stress Induced Leakage Current (SILC) and Time Zero Dielectric Breakdown (TZDB). We also