DeepScaleTool: A Tool for the Accurate Estimation of Technology Scaling in the Deep-Submicron Era

Sarangi, Satyabrata; Baas, Bevan M.

doi:10.1109/iscas51556.2021.9401196

Cited by 36 publications

(9 citation statements)

References 8 publications

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“…The resource requirement of the proposed SDE solver, including power, area, and latency consumption, is estimated based on the following assumptions: a constant reading voltage of 0.3 V [ 65 ] is used, and the digital peripherals are scaled to 32 nm technology with factors introduced in ref. [66]. Each memristor device has a read latency of 6 ns [ 20 ] and a fixed area.…”

Section: Analysis and Comparisonmentioning

confidence: 99%

Efficient Memristive Stochastic Differential Equation Solver

Dong

Primeau

Genov

et al. 2023

Advanced Intelligent Systems

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Herein, an efficient numerical solver for stochastic differential equations based on memristors is presented. The solver utilizes the stochastic switching effect in memristive devices to simulate the generation of a Brownian path and employs iterative Euler method computations within memristive crossbars. The correctness of the solution paths generated by the system is examined by solving the Black–Scholes equations and comparing the paths to analytical solutions. It is found that the absolute error of a 128‐step path is limited to an order of . Herein, the tolerance of the system is also accessed to crossbar nonidealities by comparing the numerical and analytical paths' variation in error. The numerical solver is sensitive to the variation in operating conditions, with the error increasing by , , and as the ambient temperature, wire resistance, and stuck probability of the memristor increase to extreme conditions. The solver is tested on a variety of problems to show its utility for different calculations. And, the resource consumption of the proposed structure built with existing technology is estimated and it is compared with similar iterative solvers. The solver generates a solution with the same level of accuracy from to faster than similar digital or mixed‐signal designs.

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Section: Analysis and Comparisonmentioning

confidence: 99%

Efficient Memristive Stochastic Differential Equation Solver

Dong

Primeau

Genov

et al. 2023

Advanced Intelligent Systems

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“…Note that we use Synopsys Design Compiler [122] and synthesize the additional components of our design in the target technology to obtain their execution time, power, and area. We apply the prominent technology scaling rules [106] to the configuration numbers of the PUMA architecture to ensure all of our design components are based on the same technology node.…”

Section: Implementations and Modelsmentioning

confidence: 99%

Demeter: A Fast and Energy-Efficient Food Profiler Using Hyperdimensional Computing in Memory

et al. 2022

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Food profiling is an essential step in any food monitoring system needed to prevent health risks and potential frauds in the food industry. Significant improvements in sequencing technologies are pushing food profiling to become the main computational bottleneck. State-of-the-art profilers are unfortunately too costly for food profiling. Our goal is to design a food profiler that solves the main limitations of existing profilers, namely (1) working on massive data structures and (2) incurring considerable data movement, for a real-time monitoring system. To this end, we propose Demeter, the first platform-independent framework for food profiling. Demeter overcomes the first limitation through the use of hyperdimensional computing (HDC) and efficiently performs the accurate few-species classification required in food profiling. We overcome the second limitation by the use of an in-memory hardware accelerator for Demeter (named Acc-Demeter) based on memristor devices. Acc-Demeter actualizes several domain-specific optimizations and exploits the inherent characteristics of memristors to improve the overall performance and energy consumption of Acc-Demeter. We compare Demeter's accuracy with other industrial food profilers using detailed software modeling. We synthesize Acc-Demeter's required hardware using UMC's 65nm library by considering an accurate PCM model based on silicon-based prototypes. Our evaluations demonstrate that Acc-Demeter achieves a (1) throughput improvement of 192× and 724× and (2) memory reduction of 36× and 33× compared to Kraken2 and MetaCache (2 state-of-the-art profilers), respectively, on typical food-related databases. Demeter maintains an acceptable profiling accuracy (within 2% of existing tools) and incurs a very low area overhead.

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“…All the peripheral components are scaled to 22nm technology by factors introduced in [114] and all buffers with their associated connections have energy, area and latency estimated by CACTI 7.0 [115]. For all calculations, the source resistance and line resistance of 20 Ω and 2 Ω are used respectively.…”

Section: F Power Area and Latency Requirementsmentioning

confidence: 99%

Seizure Detection and Prediction by Parallel Memristive Convolutional Neural Networks

Lammie

Dong

et al. 2022

IEEE Trans. Biomed. Circuits Syst.

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During the past two decades, epileptic seizure detection and prediction algorithms have evolved rapidly. However, despite significant performance improvements, their hardware implementation using conventional technologies, such as Complementary Metal-Oxide-Semiconductor (CMOS), in power and area-constrained settings remains a challenging task; especially when many recording channels are used. In this paper, we propose a novel low-latency parallel Convolutional Neural Network (CNN) architecture that has between 2-2,800x fewer network parameters compared to State-Of-The-Art (SOTA) CNN architectures and achieves 5-fold cross validation accuracy of 99.84% for epileptic seizure detection, and 99.01% and 97.54% for epileptic seizure prediction, when evaluated using the University of Bonn Electroencephalogram (EEG), CHB-MIT and SWEC-ETHZ seizure datasets, respectively. We subsequently implement our network onto analog crossbar arrays comprising Resistive Random-Access Memory (RRAM) devices, and provide a comprehensive benchmark by simulating, laying out, and determining hardware requirements of the CNN component of our system. To the best of our knowledge, we are the first to parallelize the execution of convolution layer kernels on separate analog crossbars to enable 2 orders of magnitude reduction in latency compared to SOTA hybrid Memristive-CMOS Deep Learning (DL) accelerators. Furthermore, we investigate the effects of non-idealities on our system and investigate Quantization Aware Training (QAT) to mitigate the performance degradation due to low Analog-to-Digital Converter (ADC)/Digital-to-Analog Converter (DAC) resolution. Finally, we propose a stuck weight offsetting methodology to mitigate performance degradation due to stuck R ON /R OFF memristor weights, recovering up to 32% accuracy, without requiring retraining. The CNN component of our platform is estimated to consume approximately 2.791W of power while occupying an area of 31.255mm2 in a 22nm FDSOI CMOS process.

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DeepScaleTool: A Tool for the Accurate Estimation of Technology Scaling in the Deep-Submicron Era

Cited by 36 publications

References 8 publications

Efficient Memristive Stochastic Differential Equation Solver

Efficient Memristive Stochastic Differential Equation Solver

Demeter: A Fast and Energy-Efficient Food Profiler Using Hyperdimensional Computing in Memory

Seizure Detection and Prediction by Parallel Memristive Convolutional Neural Networks

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