Defect analyses of selective epitaxial grown GaAs on STI patterned (0 0 1) Si substrates

Kim, S.W.; Cho, Y.D.; Shin, Chan-Soo; Park, W.K.; Kim, D.H.; Ko, Dae-Hong

doi:10.1016/j.jcrysgro.2014.01.027

Cited by 6 publications

(3 citation statements)

References 16 publications

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“…Indeed, small angle grain boundaries must be expected to originate from the small random Ge crystal tilts, analyzed in-depth in ref . These results show the superior potential of the present technique with respect to other coalescence methods widely exploited in group IV or III–V semiconductors, such as epitaxial lateral overgrowth (ELO), − which lead to defected merging regions.…”

Section: Results and Discussionmentioning

confidence: 56%

Engineered Coalescence by Annealing 3D Ge Microstructures into High-Quality Suspended Layers on Si

Salvalaglio

Bergamaschini

Isa

et al. 2015

ACS Appl. Mater. Interfaces

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The move from dimensional to functional scaling in microelectronics has led to renewed interest toward integration of Ge on Si. In this work, simulation-driven experiments leading to high-quality suspended Ge films on Si pillars are reported. Starting from an array of micrometric Ge crystals, the film is obtained by exploiting their temperature-driven coalescence across nanometric gaps. The merging process is simulated by means of a suitable surface-diffusion model within a phase-field approach. The successful comparison between experimental and simulated data demonstrates that the morphological evolution is driven purely by the lowering of surface-curvature gradients. This allows for fine control over the final morphology to be attained. At fixed annealing time and temperature, perfectly merged films are obtained from Ge crystals grown at low temperature (450 °C), whereas some void regions still persist for crystals grown at higher temperature (500 °C) due to their different initial morphology. The latter condition, however, looks very promising for possible applications. Indeed, scanning tunneling electron microscopy and high-resolution transmission electron microscopy analyses show that, at least during the first stages of merging, the developing film is free from threading dislocations. The present findings, thus, introduce a promising path to integrate Ge layers on Si with a low dislocation density.

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Section: Results and Discussionmentioning

confidence: 56%

Engineered Coalescence by Annealing 3D Ge Microstructures into High-Quality Suspended Layers on Si

Salvalaglio

Bergamaschini

Isa

et al. 2015

ACS Appl. Mater. Interfaces

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“…Twin planes are not usually observed on blanket GaAs on Si (001), where TD are the most common type of defects encountered, 9 but have often been reported in III-V ART samples. 14,28 This suggests that the layer confinement between oxide sidewalls might have a role in their formation, either because of the thermal expansion coefficient mismatch between silicon oxide and III-V layers, or because of the oxide sidewalls' roughness that locally generates stress in the growing layer, inducing the formation of twinned planes as the preferred mechanism of stress relaxation, as observed in sample 1. As a matter of fact, PV-STEM clearly shows that oxide sidewalls are not perfectly flat and do show finite roughness contributing to their slightly ragged profile.…”

Section: Resultsmentioning

confidence: 91%

GaAs on Si epitaxy by aspect ratio trapping: Analysis and reduction of defects propagating along the trench direction

Orzali¹,

Vert²,

O'Brien³

et al. 2015

Journal of Applied Physics

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The Aspect Ratio Trapping technique has been extensively evaluated for improving the quality of III-V heteroepitaxial films grown on Si, due to the potential for terminating defects at the sidewalls of SiO2 patterned trenches that enclose the growth region. However, defects propagating along the trench direction cannot be effectively confined with this technique. We studied the effect of the trench bottom geometry on the density of defects of GaAs fins, grown by metal-organic chemical vapor deposition on 300 mm Si (001) wafers inside narrow (<90 nm wide) trenches. Plan view and cross sectional Scanning Electron Microscopy and Transmission Electron Microscopy, together with High Resolution X-Ray Diffraction, were used to evaluate the crystal quality of GaAs. The prevalent defects that reach the top surface of GaAs fins are {111} twin planes propagating along the trench direction. The lowest density of twin planes, ∼8 × 108 cm−2, was achieved on “V” shaped bottom trenches, where GaAs nucleation occurs only on {111} Si planes, minimizing the interfacial energy and preventing the formation of antiphase boundaries.

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“…Both of these researches used a two-step growth method. Since then, various dislocation reduction techniques such as thermal cycle annealing (TCA) [6], strained-layer superlattices (SLS) [7,8], an amorphous Si buffer layer [9], selective evaporation of dislocated region [10], selective area or patterned growth [11], aspect ratio trapping (ART) [12,13], AlSb buffer layer [14] and compliant substrates [15] have been proposed.…”

Section: Introductionmentioning

confidence: 99%

Modified dislocation filter method: toward growth of GaAs on Si by metal organic chemical vapor deposition

Wang

et al. 2016

Appl. Phys. A

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In this paper, metamorphic growth of GaAs on (001) oriented Si substrate, with a combination method of applying dislocation filter layer (DFL) and three-step growth process, was conducted by metal organic chemical vapor deposition. The effectiveness of the multiple InAs/ GaAs self-organized quantum dot (QD) layers acting as a dislocation filter was researched in detail. And the growth conditions of the InAs QDs were optimized by theoretical calculations and experiments. A 2-lm-thick buffer layer was grown on the Si substrate with the three-step growth method according to the optimized growth conditions. Then, a 114-nm-thick DFL and a 1-lm-thick GaAs epilayer were grown. The results we obtained demonstrated that the DFL can effectively bend dislocation direction via the strain field around the QDs. The optimal structure of the DFL is composed of three-layer InAs QDs with a growth time of 55 s. The method could reduce the etch pit density from about 3 9 10 6 cm -2 to 9 9 10 5 cm -2 and improve the crystalline quality of the GaAs epilayers on Si.

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Defect analyses of selective epitaxial grown GaAs on STI patterned (0 0 1) Si substrates

Cited by 6 publications

References 16 publications

Engineered Coalescence by Annealing 3D Ge Microstructures into High-Quality Suspended Layers on Si

Engineered Coalescence by Annealing 3D Ge Microstructures into High-Quality Suspended Layers on Si

GaAs on Si epitaxy by aspect ratio trapping: Analysis and reduction of defects propagating along the trench direction

Modified dislocation filter method: toward growth of GaAs on Si by metal organic chemical vapor deposition

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