Defect and Fault Modeling Framework for STT-MRAM Testing

Abstract

STT-MRAM mass production is around the corner as major foundries worldwide invest heavily on its commercialization. To ensure high-quality STT-MRAM products, effective yet cost-efficient test solutions are of great importance. This paper presents a systematic device-aware defect and fault modeling framework for STT-MRAM to derive accurate fault models which reflect the physical defects appropriately, and thereafter optimal and high-quality test solutions. An overview and classification of manufacturing defects in STT-MRAMs are provided with an emphasis on those related to the fabrication of magnetic tunnel junction (MTJ) devices, i.e., the data-storing elements. Defects in MTJ devices need to be modeled by adjusting the affected technology parameters and subsequent electrical parameters to fully capture the defect impact on both the device's electrical and magnetic properties, whereas defects in interconnects can be modeled as linear resistors. In addition, a complete single-cell fault space and nomenclature are defined, and a systematic fault analysis methodology is proposed. To demonstrate the use of the proposed framework, resistive defects in interconnect and pinhole defects in MTJ devices are analyzed for a single 1T-1MTJ memory cell. Test solutions for detecting these defects are also discussed.

Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAM

“…In STT-MRAMs, data is stored in MTJ devices whose pre-defined resistance ranges determine the logic states '0' and '1'. Due to defects or extreme process variations, the MTJ's resistance can be outside of these ranges, as demonstrated with measurement data presented in [17]. The subscript 'n' specifies the nature of the faulty effect.…”

“…Moreover, conventional memory faults are typically described by the fault primitive notation [22], where only '0' and '1' states exist. However, in emerging non-volatile memories such as STT-MRAM and RRAM, undefined and extremely low/high resistive states may occur due to defects [17]. This calls for an expansion of memory fault space.…”

“…The resistance value represents the defect strength. This approach is also inherited to test emerging non-volatile memories such as STT-MRAM, as can be found in the prior art [8][9][10][11]17]. For any defect in the MTJ device, it is modeled as a linear resistor either in parallel to (R pd ) or in series with (R sd ) a defect-free MTJ model, as illustrated in Fig.…”

“…For example, write transition fault W0TFU= 1w0/U/means that a down-transition operation (S=1w0) turns the accessed memory cell to an undefined state (F n =U) permanently; more details about the FP notation and naming scheme can be found in [13,17]. Based on the above FP definition, the entire fault space can be redefined.…”

Impact of Magnetic Coupling and Density on STT-MRAM Performance

“…Magnetic tunnel junction (MTJ) devices are the data-storing elements in STT-MRAMs. Each MTJ device stores one-bit data in the form of binary magnetic configurations [14]. Fig.…”