Defect and fault tolerant interconnection strategies for WASP devices

Abstract

W e WSI-based devices continue to be of particular interest for applications with severe performance, s&, weight, power, cost, and reliability requirements [1]-[3], various implementation constraints in the past, including interconnect defect occurrences, have prevented their successful realization. This paper presents an investigation into defect and fault tolerant interconnect strategies for a representative WSI device, WASP (WSI Associative String Processor [3]).