Defect assessment and leakage control in Ge junctions

González, M.B.; Simoen, Eddy; Eneman, G.; Jaeger, B. De; Wang, G.; Loo, Roger; Claeys, Cor

doi:10.1016/j.mee.2014.01.012

Cited by 24 publications

(19 citation statements)

References 20 publications

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“…At lower reverse bias (V R > -1V), we observe a decrease in E A with decreasing temperature, which indicates a major contribution of TAT in our material. For TAT, the SRH generation is increased by the field enhancement factor, which in turn decreases exponentially with rising temperature [28]. It has previously been argued that TAT becomes the dominant mechanism of leakage currents for activation energies between E g /2 and 0.1 eV in Ge based junctions, which are similar to our devices [28].…”

supporting

confidence: 83%

“…The increase of  with higher V R suggests an electric field dependence of the carrier generation, as we will discuss in the following. Like in Ge, the rather small bandgap of our Si 0.06 Ge 0.94 layers (E(L c )-E( v )=0.7 eV at 300 K) can enhance tunnel processes of carriers through the bandgap in presence of a strong electric field [28].…”

mentioning

confidence: 95%

“…3, the temperature dependence of the leakage current diminishes strongly with the applied reverse bias, pointing to the action of rather weakly temperature-dependent mechanisms, such as tunneling. The leakage current activation energy E A , which is a product of all contributing transport mechanisms, is estimated by Arrhenius plots at different V R [28]; in Fig. 3 (d-f) we plot ln(J R ) vs 1/kT for different reverse biases with the Boltzmann constant, k and substrate temperature, T. For all three samples we identify three temperature regimes (T > 100°C, 25°C < T < 100°C, and T < 25°C) characterized by different slopes of the semi-logarithmic plot.…”

mentioning

confidence: 99%

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Current leakage mechanisms related to threading dislocations in Ge-rich SiGe heterostructures grown on Si(001)

Tetzner

Fischer

Skibitzki

et al. 2021

Applied Physics Letters

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The present work investigates the role of threading dislocation densities (TDD) in the low density regime on the vertical transport in Si 0.06 Ge 0.94 heterostructures integrated on Si(001). The use of unintentionally doped Si 0.06 Ge 0.94 layers enables the study of the impact of grown-in threading dislocations (TD) without interaction with processing-induced defects originating e.g. from dopant implantation. The studied heterolayers, while equal in composition, the degree of strain relaxation, and the thickness, feature three different values for the TDD: 3×10 6 , 9×10 6 and 2×10 7 cm -2 . Current-voltage measurements reveal that leakage currents do not scale linearly with TDD. The temperature dependence of the leakage currents suggests a strong contribution of field-enhanced carrier generation to the current transport, with the trap-assisted tunneling via TD-induced defect states identified as the dominant transport mechanism at room temperature. At lower temperature and at high electric fields, direct band-to-band tunneling without direct interaction with defect levels becomes the dominating type of transport. Leakage currents related to emission from mid-gap traps by the Shockley-Read-Hall (SRH) generation is observed at higher temperatures (>100 °C). Here, we see a reduced contribution coming from SRH in our material, featuring the minimal TDD (3×10 6 cm -2 ), which we attribute to a reduction in point defect clusters trapped in the TD strain fields.

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supporting

confidence: 83%

mentioning

confidence: 95%

mentioning

confidence: 99%

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Current leakage mechanisms related to threading dislocations in Ge-rich SiGe heterostructures grown on Si(001)

Tetzner

Fischer

Skibitzki

et al. 2021

Applied Physics Letters

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“…Also the corresponding gate overdrive voltage (V GT ) is included, which represents the difference between the gate (V GS ) and threshold (V T ) voltages, and the V GS value for each device during the temperature evaluation. According to the literature, the activation energy of a threading dislocation (TD) in Ge is between ∼0.26-0.33 eV above the valence band, as derived from Deep-Level Transient Spectroscopy (DLTS) [15]. Although the E values in Table I are derived from LFN measurements and there is some scatter for the different processes, one might correlate the defect origin with TDs.…”

Section: Table I Device Parameters For Different Ge Pfinfet Sti Processesmentioning

confidence: 99%

GR-Noise Characterization of Ge pFinFETs With STI First and STI Last Processes

Oliveira

Simoen

Mitard

et al. 2016

IEEE Electron Device Lett.

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This lettercharacterizes the generationrecombination noise of Ge pFinFETs, for three different integration schemes: shallow trench isolation (STI) first strained devices; STI last for relaxed and strained ones. It is shown that many Lorentzians exhibit a V GS -independent and thermally activated characteristic frequency. This points out that the responsible defects are located inside the fin and they are found for all studied process conditions. One type of defect with a time constant value of 10 ms at room temperature is process-independent. Regarding the defects, their activation energies and hole capture cross sections have been extracted for fin widths varying from planarlike devices to narrow ones. It is shown that the STI last strained and relaxed devices yield a surface trap density three orders of magnitude above the typical value obtained for a blanket wafer.

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“…This suggests that the extracted activation energy of 0.3 eV is not the only mechanism leading to the measured total reverse current. Because of the strong bias dependence of the total reverse current, effects such as trap-assisted tunneling or even band-to-band tunneling can be expected [31].…”

Section: Temperature-dependent Current-voltage Characteristicsmentioning

confidence: 99%

Electrical characterization of p-GeSn/n-Ge diodes with interface traps under dc and ac regimes

Baert

Gupta

Gencarelli

et al. 2015

Solid-State Electronics

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In this work, the electrical properties of p-GeSn/n-Ge diodes are investigated in order to assess the impact of defects at the interface between Ge and GeSn using temperature-dependent current-voltage and capacitance-voltage measurements. These structures are made from GeSn epitaxial layers grown by CVD on Ge with in-situ doping by Boron. As results, an average ideality factor of 1.2 has been determined and an activation energy comprised between 0.28 eV and 0.30 eV has been extracted from the temperature dependence of the reverse-bias current. Based on the comparison with numerical results obtained from device simulations, we explain this activation energy by the presence of traps located near the GeSn/Ge interface.

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Defect assessment and leakage control in Ge junctions

Cited by 24 publications

References 20 publications

Current leakage mechanisms related to threading dislocations in Ge-rich SiGe heterostructures grown on Si(001)

Current leakage mechanisms related to threading dislocations in Ge-rich SiGe heterostructures grown on Si(001)

GR-Noise Characterization of Ge pFinFETs With STI First and STI Last Processes

Electrical characterization of p-GeSn/n-Ge diodes with interface traps under dc and ac regimes

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