Defect-aware methodology for low-power scan-based VLSI testing

Priya, A. Swetha

doi:10.1109/pccctsg.2015.7503931

Cited by 7 publications

(1 citation statement)

References 19 publications

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“…The technique has shown a reduction in average shift and average capture power. Techniques presented in [35], [36] also use different filling methods and choose the pattern with lesser switching activity.…”

Section: Evaluating and Choosing X-fillmentioning

confidence: 99%

A survey of scan-capture power reduction techniques

Sontakke,

Dickhoff

2023

IJECE

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With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing.

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Section: Evaluating and Choosing X-fillmentioning

confidence: 99%