Defect-based test optimization for analog/RF circuits for near-zero DPPM applications

Abstract

Abstract-Analog circuits are often tested based on their specifications. While specification-based testing ensures the initial product quality, full testing is often not possible in high volume production. Moreover, even full specification-based testing cannot guarantee that the circuit does not contain any physical defects. Some application domains require near-zero defect levels independent of whether the specifications are met. In this work, we present a defect based test optimization method focusing on defective parts per million (DPPM) minimization. We extract potential defects through inductive fault analysis (IFA) and reduce the number of tests without degrading the test quality. In order to achieve near zero DPPM, we employ outlier analysis to identify defective circuits that cannot be identified using specification based methods. Simulation results on an LNA show that DPPM is reduced down to 0 at a cost of 0.2% yield loss with the proposed method.

Forward prediction based on wafer sort data — A case study

“…There have been other works that analyze wafer probe measurements for improving test quality and reduce the DPPM rate for extremely high quality devices. For example, the work in [12] created a defect density fault model using simulated opens, shorts and pin-hole defects in order to improve test quality and reduce the DPPM rate of an analog device.…”