Defect classes-an overdue paradigm for CMOS IC testing

Abstract

The IC test industry has struggled .for more than 30 years to establish a test approach that would guarantee a low defect level to the customer. We propose a comprehensive strategy for testing CMOS ICs that uses defect classes based on measured defect electrilxd properti'es. Defect classes differ from traditional fault models. Our defect class approach requires that the test strategy match the defect electrical properties, while fault models require that IC defects match the fault definition. We use data from Sandia Labs failure analysis and lest facilities and from public literature [l-601. We describe test pattern requirements for each defect class and propose a test paradigm.

Application of fuzzy logic in resistive fault modeling and simulation

“…As presented by [23], [2], and [1] the resistance of the bridging faults may vary between several ohms to several kilo ohms depending strongly on the layout details, technology and fabrication process. However, the resistance of 0.5-2 K provided satisfactory results in test of digital circuits [23].…”

“…Unfortunately, such defects represent a significant fraction of faults in complex digital circuits [1], [2]; thus, it is vital to investigate their presence, effects, and detectability.…”

Diagnosis of Full Open Defects in Interconnecting Lines

“…PEN defects are frequently occurring in nowadays CMOS technologies [1] [2]. They have been traditionally modelled as a resistance inserted between the two disconnected physical points in the line having the defect.…”

Detection probabilities of interconnect breaks: an analysis

“…The three classes of defects that can occur during the manufacturing process of an integrated circuit (IC) are bridge defects, break (open circuit) defects, and parametric delay defects (1). This paper is concerned with defects of the second type (i.e., breaks).…”