Diagnosis of Full Open Defects in Interconnecting Lines

Abstract

Abstract-

Impact of gate tunnelling leakage on CMOS circuits with full open defects

“…In this situation, the response of the circuit is known to depend on several factors [4] such as (a) the capacitances between the floating line and its neighbouring lines of the semiconductor structures, (b) the parasitic capacitances of the transistors driven by the floating line and (c) the trapped charge in the oxide. Moreover, the logic response of the circuit to the floating voltage depends on the logic input threshold voltage of the downstream gates for each particular test pattern (Byzantine effect).…”

“…The majority of opens isolate the line completely and are referred to as strong or full opens [1]. Over recent decades, research effort has been devoted to the characterisation of CMOS circuits with open defects [2][3][4]. However, relatively little attention has been given to opens below the range of sub-180 nm feature size.…”

Investigation into voltage and process variation-aware manufacturing test

“…Such high resistances must be considered as full opens. Furthermore, complete breaks have been found in diagnosis of faulty chips [37,70,71,72]. Full opens are as important to consider as resistive opens according to [37].…”

“…A vital component of the fault model for full opens is the location of the defect, which has been considered in [85,118,72]. A full open defect can occur anywhere along the nets of the design, within a logic gate or on the interconnect.…”

“…A full open defect can occur anywhere along the nets of the design, within a logic gate or on the interconnect. The study in [85] proved useful in several diagnosis and fault analysis studies [85,119,118,72]. The defect coverage metric is typically defined as the ratio of detected faulty behaviours and the number of considered faulty behaviours.…”