Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs

Memory Testing and Repairing Using MBIST with Complete Programmability

“…A fault model is a systematic and precise representation of physical faults in a form suitable for simulation and test generation [11]. Applying the reduced functional model, SRAM faults can be classified as follows:…”

“…It implements test algorithm programmability at low cost, by extracting the different levels of hierarchy of the test algorithm and associating a hardware bloc to each of them, resulting on low cost hardware. It enables low-cost implementation of full-data Programmability by adapting the transparent memory test approach [10][11][12][13][14][15][16] in a manner that uses the memory under test for programming the test data. As stated in the introduction, the aim of this paper is to extent the above programmable BIST scheme to enable programming the address sequence, thus enabling programmability of all components of memory test: test algorithm; test data; address sequence.…”

“…The main challenge when implementing complete programmability of the address sequence used concerns the large amount of data that have to be programmed (here the complete memory address space) and the associated high hardware cost. We resolve this problem by adapting the transparent BIST scheme [10][11][12][13][14][15][16] in a way enabling storing the address sequence in the memory under test and using it for testing the memory.…”

Power supply signal calibration techniques for improving detection resolution to hardware Trojans

“…In this paper, we investigate four signal calibration techniques, called DC for I DDQ -based, AS for AC-sample-based (first proposed in [17]), AA for AC-area-based and AW for AC-waveform-based, and compare their effectiveness on reducing the adverse effects of PE variations against a fifth technique called NC, i.e., no signal calibration. All methods (except NC) make use of the calibration test data to define a transformation matrix.…”

Multivariate model for test response analysis

“…Since the parametric variation and the measurement bias have become integral part of VLSI manufacturing and test environment, the paradigm of test response analysis has shifted from univariate [1] to multivariate analysis [2]. In a univariate analysis, only one test response variable is analyzed at a time.…”