2014

DOI: 10.9790/2834-09228083

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Memory Testing and Repairing Using MBIST with Complete Programmability

Darsi Koteswaramma¹,

K.Murali Krishna²,

et al.

Abstract: : Most of the System-on-Chip (SoC)

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Cited by 3 publications

References 9 publications

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BIST Architecture for Multiple RAMs in SoC

John¹,

2017

Procedia Computer Science

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No abstract

BIST Architecture for Multiple RAMs in SoC

John¹,

2017

Procedia Computer Science

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No abstract

An informational approach to quantizing the effectiveness of test data arrays for static memory devices

¹

,

²

,

³

et al. 2020

IOP Conf. Ser.: Mater. Sci. Eng.

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While testing of the Static Random Access Memory (SRAM) the effective detection of potential faults is mostly determined by the structure and the algorithm of test arrays of data generation. This article proposes a multiplicative indicator W, which allows us to quantify the quality of test arrays of data. It is necessary to represent test arrays of data as a binary matrix, where each column corresponds to a certain bit of SRAM, and the rows correspond to test patterns. In this case, the process of sequential formation of test patterns is identified with the percolation process on a rectangular grid. It is assumed that percolation occurs at the moment when the maximization of the binary antagonisms both on the rows and on the columns of the binary matrix is provided. In this case, the binary sequences in all columns of the matrix must be different. Preliminary experimental data allows to suggest that the evaluation of the quality of test arrays of data based on the proposed indicator W can simultaneously be considered as the maximum efficiency of detecting a certain class of potential SRAM faults in a certain order of reading test data.

SRAM Memory Built in Self-Test using MARCH Algorithm

²

,

et al. 2022

2022 International Conference on Augmented Intelligence and Sustainable Systems (ICAISS)

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