25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014) 2014
DOI: 10.1109/asmc.2014.6847011
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Defect engineering for carrier lifetime control in high voltage GaAs power diodes

Abstract: The paper considers the physical basis for the technique of controllable defect formation at heterointerfaces and in the bulk of epitaxial GaAs layers in the process of isovalent doping. Results of studying crystal defects and their rearrangement depending on the isovalent doping modes in the process of epitaxial growth are presented. The main aspects of the defect influence on the charge carrier lifetime as well as on the diode structure blocking voltage are analyzed. Particular cases of the developed techniq… Show more

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Cited by 13 publications
(14 citation statements)
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“…It has been found previously [7] that, when layers for which the combination of the lattice mismatch and thicknesses is such that elastic stresses are partly relaxed and mismatch dislocations are thereby formed (see below), the composition of the solid solution of a layer tends to be the closest to that in equilibrium. This was confirmed by X-ray microanalysis on a Camebax installation for In x Ga 1-x As layers in which elastic stresses are partly relaxed via formation of a network of linear mismatch dislocations revealed by X-ray topography [7]. Diode chip samples had a form of «mesa» with round base which was obtained by chemical etching of active layers up to substrate around contact pads.…”
Section: Sample Fabricationmentioning
confidence: 97%
“…It has been found previously [7] that, when layers for which the combination of the lattice mismatch and thicknesses is such that elastic stresses are partly relaxed and mismatch dislocations are thereby formed (see below), the composition of the solid solution of a layer tends to be the closest to that in equilibrium. This was confirmed by X-ray microanalysis on a Camebax installation for In x Ga 1-x As layers in which elastic stresses are partly relaxed via formation of a network of linear mismatch dislocations revealed by X-ray topography [7]. Diode chip samples had a form of «mesa» with round base which was obtained by chemical etching of active layers up to substrate around contact pads.…”
Section: Sample Fabricationmentioning
confidence: 97%
“…Сильно легированные теллуром n + -GaAs слои эмиттеров диод-ных структур выращивались в графитовой поршневой кассете. Типичное распределение концентрации свобод-ных носителей заряда по толщине GaAs или InGaAs p−i−n-структур и описание методики изготовления таких структур представлены в [2,4]. Профили рас-пределения свободных носителей заряда получали при послойном стравливании структуры из вольт-емкостных зависимостей обратносмещенного барьера Шоттки с помощью ртутного зонда.…”
Section: изготовлениеunclassified
“…К настоящему времени для создания высоковольтных GaAs p−i−n-структур в основном используется ме-тод жидкофазной эпитаксии (ЖФЭ) из ограниченного раствора−расплава Ga−As с контролируемым распреде-лением остаточных примесей [1][2][3][4]. Как было отмечено в работе [5], существенное влияние на временные ха-рактеристики арсенид-галлиевых диодов (время жизни неравновесных носителей заряда и нарастания пере-падов напряжения), а также на блокируемое диодны-ми структурами напряжение должны оказывать дефек-ты и интерфейсные состояния с глубокими уровнями (ГУ), образующиеся в процессе эпитаксиального ро-ста p−i−n-структур.…”
Section: Introductionunclassified
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