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A study of deep levels in InGaAs/GaAs and GaAsSb/GaAs p0–i–n0 heterostructures with misfit dislocations and identification of the effective defects responsible for the significant (by up to a factor of 100) decrease in the relaxation time of nonequilibrium carriers in the base layers (and in the related reverse recovery time) of InGaAs/GaAs and GaAsSb/GaAs high-voltage power p-i-n diodes is reported. Experimental capacitance–voltage characteristics and deep-level transient spectroscopy spectra of p+–p0–i–n0–n+ homostructures based on undoped GaAs layers without misfit dislocations and InGaAs/GaAs and GaAsSb/GaAs heterostructures with a homogeneous network of misfit dislocations, all grown by liquid-phase epitaxy, are analyzed. Acceptor defects with deep levels HL2 and HL5 are identified in GaAs epitaxial p0 and n0 layers. Dislocation-related electron and hole deep traps designated as ED1 and HD3 are detected in InGaAs/GaAs and GaAsSb/GaAs heterostructures. The effective recombination centers in the heterostructure layers, to which we attribute the substantial decrease in the relaxation time of nonequilibrium carriers in the base layers of p-i-n diodes, are dislocation-related hole traps that are similar to HD3 and have the following parameters: thermal activation energy Et = 845 meV, carrier capture cross-section σp = 1.33 × 10−12 cm2, concentration Nt = 3.80 × 1014 cm−3 for InGaAs/GaAs and Et = 848 meV, σp = 2.73 × 10−12 cm2, and Nt = 2.40 × 1014 cm−3 for the GaAsSb/GaAs heterostructure. The relaxation time of the concentration of nonequilibrium carriers in the presence of dislocation-related deep acceptor traps similar to HD3 was estimated to be 1.1 × 10−10 and 8.5 × 10−11 s for, respectively, the InGaAs/GaAs and GaAsSb/GaAs heterostructures and 8.9 × 10−7 s for the GaAs homostructure. These data correspond to the relaxation times of nonequilibrium carriers in the base layers of GaAs, InGaAs/GaAs, and GaAsSb/GaAs high-voltage power p-i-n diodes.

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The paper considers the physical basis for the technique of controllable defect formation at heterointerfaces and in the bulk of epitaxial GaAs layers in the process of isovalent doping. Results of studying crystal defects and their rearrangement depending on the isovalent doping modes in the process of epitaxial growth are presented. The main aspects of the defect influence on the charge carrier lifetime as well as on the diode structure blocking voltage are analyzed. Particular cases of the developed technique application for controllable defect formation in fabricating such GaAs-based devices as Hyper Fast Recovery Epitaxial Diodes and Drift Step Recovery Diodes are considered.Keywords-gallium arsenide, liquid phase epitaxy, crystal defects, charge carrier lifetime, isovalent doping, turn-off time, fast recovery epitaxial diode, rise time, step recovery diode.

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