Defect-oriented cell-internal testing

Hapke, F.; Redemund, W.; Schloeffel, J.; Krenz-Baath, Rene; Glowatz, A.; Wittke, Michael; Hashempour, H.; Eichenberger, S.

doi:10.1109/test.2010.5699229

Cited by 39 publications

(20 citation statements)

References 14 publications

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“…In [9] we presented a method focusing on cell-internal bridges across a wide range of bridge resistor values, and a second method concentrating on library cell- [10]. Recently, in [11] we presented first production test results for slowspeed CA, GE and TR N-detect tests that showed CA patterns are the most efficient method to detect other undetected defects.…”

Section: Previous Workmentioning

confidence: 99%

“…These fault models are insufficient for today's technologies that require low defect rates. In our previous work, in which we introduced the cell-aware (CA) methodology [8], [9], we showed that the classical SA, TR, ND, and GE approaches do not target all real defects in library cells or are too expensive for production tests. First production test results were presented in [11] for slowspeed CA, GE, and TR N-detect tests.…”

Section: Introductionmentioning

confidence: 99%

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Cell-aware Production test results from a 32-nm notebook processor

Hapke¹,

Reese

Rivers

et al. 2012

2012 IEEE International Test Conference

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This paper describes a new approach for significantly improving overall defect coverage for CMOS-based designs. We present results from a defect-oriented cellaware (CA) library characterization and patterngeneration flow and its application to 1,900 cells of a 32-nm technology. The CA flow enabled us to detect cell-internal bridges and opens that caused static, gross-delay, and small-delay defects. We present highvolume production test results from a 32-nm notebook processor to which CA test patterns were applied, including the defect rate reduction in PPM that was achieved after testing 800,000 parts. We also present cell-internal diagnosis and physical failure analysis results from one failing part.

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Section: Previous Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Cell-aware Production test results from a 32-nm notebook processor

Hapke¹,

Reese

Rivers

et al. 2012

2012 IEEE International Test Conference

Self Cite

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show abstract

“…The complete analysis flow is shown in Figure 1. For this small-delay test analysis, we first perform an exhaustive one-cycle analog fault simulation to calculate the cellaware gross-delay detectable bridge defects as presented in [5] and [6]. For all undetected bridge defects from this first step, we then perform an exhaustive two-cycle analog fault simulation for all stimuli, which produces an output edge in the fault-free case.…”

Section: Small-delay Test Analysismentioning

confidence: 99%

“…Our previous work [5], [6] showed that the classical stuck-at approach is insufficient for faults and defects within cells. We proved that it is necessary to step from inter-cell fault models to intra-cell fault models.…”

Section: Introductionmentioning

confidence: 99%

Cell-aware analysis for small-delay effects and production test results from different fault models

Hapke¹,

Schloeffel²,

Redemund³

et al. 2011

2011 IEEE International Test Conference

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This paper focuses on a new approach to significantly improve the overall defect coverage for CMOS-based designs with the final goal to eliminate any system-level test. This methodology describes the pattern generation flow for detecting cell-internal small-delay defects caused by cell-internal resistive bridges. Results have been evaluated on 1,900 library cells of a 32-nm technology. First production test results are presented from evaluating additional defect detections achieved with different fault models on a 45-nm design.

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“…We compared CAT and GE patterns in [21]. CAT has proven to be effective in detecting cell-internal defects, as demonstrated through high-volume production test results presented in [22]- [27]. In these cases, stateof-the-art fault models were shown to be insufficient; only CAT achieved the demanded low defective-parts-per-million (DPPM) rates.…”

mentioning

confidence: 99%

Cell-Aware Test

Hapke¹,

Redemund²,

Glowatz³

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

159

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This paper describes the new cell-aware test (CAT) approach, which enables a transistor-level and defect-based ATPG on full CMOS-based designs to significantly reduce the defect rate of manufactured ICs, including FinFET technologies. We present results from a defect-oriented CAT fault model generation for 1,940 standard library cells, as well as the application of CAT to several industrial designs. We present high volume production test results from a 32 nm notebook processor and from a 350 nm automotive design, including the achieved defect rate reduction in defective-parts-per-million. We also present CAT diagnosis and physical failure analysis results from one failing part and give an outlook for using the functionality for quickly ramping up the yield in advanced technology nodes.Index Terms-Automatic test pattern generation, cell-aware test, defect-based test, defective parts, design for testability, failure analysis, FinFET test, logic testing, test data compression, transistor-level test.

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Defect-oriented cell-internal testing

Cited by 39 publications

References 14 publications

Cell-aware Production test results from a 32-nm notebook processor

Cell-aware Production test results from a 32-nm notebook processor

Cell-aware analysis for small-delay effects and production test results from different fault models

Cell-Aware Test

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