Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL

Abstract

The validation of high-quality tests requires Defect-Oriented (DO) fault simulation. The purpose of this paper is to propose a methodology for mixed-level DO fault simulation, using HDL. A novel tool, veriDOFS, is introduced. Structural zooming is performed only for the system module in which the faults are injected. Verilog models for bridging and line open defects are proposed for intra-gate and inter-gate faults. Design hierarchy is exploited, by pre-computing a test view of each cell in a library. The good trade-off accuracy / tractability, as well as the computational efficiency of the new tool are demonstrated by means of structural benchmarks up to 100,000 transistors and 300,000 realistic faults.

Standard CAD Tool-Based Method for Simulation of Laser-Induced Faults in Large-Scale Circuits

“…To the best of our knowledge, among the existent fault simulators [6,12,18,21,24], the most recent one is [19], which is based on the open-source Lifting [1]. The major issue with these fault simulators is that they rely on electrical models [8,11,25] that are technology dependent.…”

Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level

“…• Multi-level simulation of switch-level and gate-level representations [9] • Serial simulation of structural faults in mixed-level gatelevel/RTL models with event-based simulators [10,11] • Mixed-level fault-simulation of gate-level and RTL using concurrent simulation [12,13] • Simulation of structural faults in mixed-level gatelevel/architectural-level simulations with symbolic simulation in the architecture-level model [14,15] • Serial fault injections performed at RT-level with error propagation at system-level [5] • Injection of structural faults into mixed gate-level/highlevel SystemC models [16] • Mutator-based injection of faults into RTL and transaction-level models [17] The work presented here is the first approach that efficiently implements concurrent multi-level fault simulation across gate-and transaction-level in an integrated simulation environment. Our work is based on a structural fault model with an efficient concurrent fault simulator at gate-level.…”