Defect reduction in Cu dual damascene process using short-loop test structures

Abstract

This paper outlines the defect reduction measures performed during the development of a 130-nm Cu dual-damascene process. The test methodology, using short-loop test structures, included defect tracing, overlaying defect data and electrical measurement data, physical analyses based on these results, and analyses of defect size distribution. While the defect size distributions for large-scale integration processes are considered to depend on , the distribution for the Cu dual-damascene process is found to be different and is instead characterized by a cumulative distribution described by the composition of several Lorentzian functions. Using these procedures, defect densities were successfully reduced by 50% in half the time taken previously and without the need for actual products.

Identification and Characterization of a Subtle Bump Defect Formed Upon Organic Mandrel in a Self-Aligned Double Patterning Process

“…Nevertheless, the yield ramping is still the central challenge in the SADP technology (1,3). Strategy to improve so is focused on the defect detection and reduction throughout the manufacturing process flow (3,4). In this study, a conventional SADP manufacturing flow is given as below: (i) photo-resist (PR) lithography, (ii) bottom antireflective coating (BARC) etch to form PR/BARC mandrel, (iii) room temperature atomic layer oxide deposition (RT-ALD oxide) on the organic mandrel, (iv) RT-ALD oxide spacer etch and (v) poly-Si hard mask etch.…”