Defect-tolerant demultiplexer circuits based on threshold logic and coding

Abstract

A defect-tolerant design is presented for a demultiplexer circuit that is based on threshold logic. The design uses coding both to handle (i.e., tolerate) defects in the circuit and to improve the voltage margin in its gates. The following model is assumed for the defects: configured junctions can become either stuck open or stuck closed, and non-configured junctions can become shorted. Two realizations of the circuit are presented: one using conventional transistor circuitry, and the other using nanoscale components and wiring. The design presented in this paper demonstrates how a standard digital building-block circuit-a demultiplexer-can be efficiently protected against several types of defect simultaneously.

Physical Fault Tolerance of Nanoelectronics

“…von Neumann proposed [10] fault-tolerant architectures for computing with faulty components, a concept now extended to triplicate modular redundancy at the system level [11] and gate-level quantum error correction [12][13][14]. Fault-tolerant architectures are effective in correcting physical errors in nanoscale devices [15][16][17], but is the fault-tolerant architecture approach optimal for maximizing functional density? It has been postulated that topological excitations of many-body systems provide inherent physical fault tolerance for quantum computation [18,19] in lieu of architectural redundancies.…”