This paper reports new and practical design schemes for nanoscale integrated circuits, in order to ensure their func tionality despite noise and faults. The proposed designs use a new cyclic binary decision diagram (BOD). The cyclic BOD enables the conventional BOD design algorithms by using feedback and Markov Random Field (MRF) model of logic gates. By applying the feedback and MRF premises, effective and robust design can be achieved. Simulations are reported to justify the fault tolerance and noise-immunity of the proposed schemes. I. IN T RODUC TIONNoise-mitigation and noise-tolerance are two distinct ap proaches to handle noise in nanoscaled ICs. Noise mitiga tion requires complex temperature assessment and consequent circuitry redundancy. We focus on the designs, which are inherently tolerant to noise and errors. In particular, in [1], [2], we studied neuromorphic models based on Hopfield networks with Boltzmann updating rules. These models exhibit noise tolerance. However, depending on the signal-to-noise ratio, thousands iterations are required in order to ensure the stability of these networks with corresponding states and outputs.In this paper, we aim at achieving noise-tolerance by using Markov Random Field (MRF). The MRF, unlike the Hopfield model, does not require time-redundancy. It considers inputs and outputs of circuits as random variables. There is no notion of a correct logic state in the MRF model, as the states are determined using the probability distribution of signals. The correct states are those, which maximize the joint probability distribution of random variables. In circuit implementation, this results in creating a feedback, which reinforces the most probabilistically correct state and reduces the error of incorrect (less probable) outputs. In [3], an MRF model of logic gates is proposed using a reinforcement and updating by means of a feedback. The CMOS implementation of the modified MRF model was reported in [4]. Instead of using logic gates, we employ bidirectional switches in the proposed design solution. Such circuits are often modeled using the Shannon expansion with the corresponding graph-based implementation, which implies a Binary Decision Diagram (BDD). To implement the premise of feedback, we introduce a new type of decision diagrams, namely, a cyclic BDD. II. THEORETICAL BASICS Binary decision tree An n-Ievel Binary Decision Tree (BDT) represents a logic function of n variables. A BDT is a rooted directed graph with two types of vertices: non-terminal nodes (on levels 1 to n of the tree), and terminal nodes, corresponding to the function values. A BDD is a rooted directed graph, obtained from a BDT by reduction rules [5]. Binary decision diagram A BDD corresponds to a representation of a discrete func tion by means of the Shannon expansion. They are easily mapped to technology, because the circuit layout of a circuit is directly determined by the shape of the BDD, and each node corresponds to a I-to-2 demultiplexer (DEMUX) or a 2-to-1 multiplexer (MUX). An example of a ...

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Probabilistic AND/EXOR networks have been defined, in the past, as a class of Reed-Muller circuits, which operate on random signals. In contemporary logic network design, it is classified as behavioral notation of probabilistic logic gates and networks. In this paper, we introduce additional notations of probabilistic AND/EXOR networks: belief propagation, stochastic, decision diagram, neuromorphic models, and Markov random field model. Probabilistic logic networks, and, in particular, probabilistic AND/EXOR networks, known as turbo-decoders (used in cell phones and iPhone) are in demand in the coding theory. Another example is intelligent decision support in banking and security applications. We argue that there are two types of probabilistic networks: traditional logic networks assuming random signals, and belief propagation networks. We propose the taxonomy for this design, and provide the results of experimental study. In addition, we show that in forthcoming technologies, in particular, molecular electronics, probabilistic computing is the platform for developing the devices and systems for low-power low-precise data processing.

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