Defect-tolerant fpga switch block and connection block with fine-grain redundancy for yield enhancement

Abstract

Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate multiple defects [6]. We propose a number of changes to the detailed routing architecture of island-style FPGAs to tolerate multiple random, distributed interconnect defects without re-routing and with minimal impact on signal timing. Our scheme is a user option prebuilt into an architecture, requiring +11% area for additional multiplexers. Unused (spare) wiring tracks are also needed, bringing total overhead to 24% to tolerate stuck-at or open faults, or 34% to include bridging. User circuits that do not fully stress the routing network already have these tracks freely available. The delay penalty is programmable: 5-10% if defect rates are expected to be sufficiently low, but can be as high as 25% if defect rates are high. Our schemes can tolerate more than 10 interconnect defects for large array sizes of 128 × 128. Unlike row/column redundancy schemes, our schemes are scalable: they naturally tolerate more defects as the FPGA array size increases. This work is the first detailed analysis of fine-grained defect-tolerant schemes in FPGAs.

FPGA Architecture: Survey and Challenges

“…With another set of switches, connections can be shifted to avoid defective routing segments. The area and delay overheads of this approach on a modern architecture have been estimated to be 25%-40% and 15%-25%, respectively [240]. This approach is particularly interesting because in defect-free devices the additional switches can be used to provide additional flexibility and potentially improved performance which lowers the effective overheads of such schemes.…”

“…An alternative to the coarse-grained approach of adding complete rows or columns of logic is a more fine-grained approach of adding additional switches throughout the FPGA interconnect [73,240]. With another set of switches, connections can be shifted to avoid defective routing segments.…”

Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGA

“…To adapt the Fine Grain Redundancy technique (FGR) [12] for the Sbox of a Mesh of Clusters architecture, four levels of multiplexers (Mux) are added around all the MSB of the Sbox. As the FGR technique is useless if the nearest multiplexer is already used by another input, the Improved Fine Grain Redundancy (IFGR) was proposed in [18] to avoid this kind of conflicts. This solution doubles the number of outputs per multiplexer that allows to use the second output in case of defect on the other one.…”

“…Hardware-based techniques can be implemented in FPGAs to increase their reliability. The studies in [12] and [13] showed that using hardware redundancy on the top level of the FPGA requires more area to tolerate the same number of defects than a hardware redundancy applied inside local interconnect. As theses techniques increase significantly the FPGA area, it is therefore necessary to apply a local redundancy inside the FPGA depending on the criticality of each block.…”

Evolving Redundant Structures for Reliable Circuits - Lessons Learned

“…adding extra local routing between two switch blocks. If a defective wire is found, the redundant one takes over its functionality [6,19].…”