Deformation Induced Holes in Ge-Rich SiGe-on-Insulator and Ge-on-Insulator Substrates Fabricated by Ge Condensation Process

Abstract

Electrical properties of Ge-rich SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) structures fabricated by Ge condensation process have been studied. The SGOI and GOI structures for Ge composition, xGe, larger than 0.4 exhibit p-type conduction. The hole density is found to rapidly increase from 1016 to 1018 cm-3 with an increase in xGe during the Ge condensation and to decrease down to low-1017 cm-3 when xGe reaches unity. Analyses of scanning spreading resistance microscopy have directly revealed that the SGOI and GOI structures are highly conductive along the crosshatched slip bands formed during the condensation, meaning that the holes are induced along the slip bands in SGOI and GOI films. As a result, it is concluded that the hole induced during the Ge condensation is strongly associated with the slip band formation.

Challenges and opportunities in advanced Ge pMOSFETs

“…In addition, the effective mobility versus effective electric field (E eff ) shows opposite behavior for the two substrate orientations [36]. The remarkable (and favorable) increase of m eff with E eff for Ge (110) points to a different dominant scattering mechanism, with less surface roughness scattering and different phonon scattering.…”

“…On (111) substrates no benefit is expected for m h [33], unless compressive strain is applied [32]. On the other hand, a clear mobility improvement of unstrained Ge (110) pMOSFETs with respect to Si (110) has been demonstrated [28,31,[34][35][36], yielding values in the range of 230-300 cm 2 /Vs for m h (Table 1). This is an enhancement factor of 3 and 1.5 against the (100) Si universal hole mobility and the (110) SOI effective hole mobility, respectively [35].…”

“…This is related to the corresponding anisotropic surface reconstruction, which may be responsible for the introduction of a large density of growth twins in epitaxial layers on (110) Si. Recently, however, it has been shown that the introduction of Sn atoms results in high-quality, smooth Ge 1 À x Sn x (110) layers (x¼0.048) on (110) Ge [37].…”

“…One is the high acceptor concentration which is typically observed [109][110][111][112]. This problem also exists for GeOI wafers fabricated by the transfer of thick Ge epitaxial layers [54,113] and gives rise to large back-channel conduction in pMOSFETs, fabricated in such material.…”

“…This means that one has to consider processing on non-standard silicon substrates for planar devices. This is even more relevant for Fin-or vertical type of structures, where the major part of the sidewall conduction occurs along (110)/ [110] non-standard orientations. In addition, compressive strain will be required for Ge to exceed the hole mobility of strained silicon (sSi).…”