A strained Ge-on-insulator (GOI) structure with a 7-nm-thick Ge layer was fabricated for applications to high-speed transistors. The GOI layer was formed by thermal oxidation of a strained SiGe layer grown epitaxially on a silicon-on-insulator (SOI) wafer. In transmission electron microscopy measurements, the obtained GOI layer exhibited a single-crystal structure with the identical orientation to an original SOI substrate and a smooth Ge/SiO2 interface. The rms of the surface roughness of the GOI layer was evaluated to be 0.4 nm by atomic force microscopy. The residual Si fraction in the GOI layer was estimated to be lower than the detection limit of Raman spectroscopy of 0.5% and also than the electron energy loss spectroscope measurements of 3%. It was found that the obtained GOI layer was compressively strained with a strain of 1.1%, which was estimated by the Raman spectroscopy. Judging from the observed crystal quality and the strain value, this technique is promising for fabrication of high-mobility strained Ge channel of high-performance GOI metal–insulator–semiconductor (MIS) transistors.

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Electrical properties of Ge-rich SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) structures fabricated by Ge condensation process have been studied. The SGOI and GOI structures for Ge composition, xGe, larger than 0.4 exhibit p-type conduction. The hole density is found to rapidly increase from 1016 to 1018 cm-3 with an increase in xGe during the Ge condensation and to decrease down to low-1017 cm-3 when xGe reaches unity. Analyses of scanning spreading resistance microscopy have directly revealed that the SGOI and GOI structures are highly conductive along the crosshatched slip bands formed during the condensation, meaning that the holes are induced along the slip bands in SGOI and GOI films. As a result, it is concluded that the hole induced during the Ge condensation is strongly associated with the slip band formation.