Delamination-induced dielectric breakdown in Cu/low-k interconnects

Abstract

Delamination at an interface with the weakest adhesion strength, which is found to be between the SiC(N) capping layer and the SiOCH low-k dielectric, is a potential failure mechanism contributing to time-dependent dielectric breakdown (TDDB) reliability. Bond breaking at that interface is believed to be driven by a field-enhanced thermal process and catalyzed by leakage current through the capping layer based on physical analyses and TDDB measurements. Delamination is found to be easier in terminated tips and corners than in parallel comb lines due to the layout orientation of the Cu lines. Moreover, TDDB activation energy E a can be an indicator of the ease of delamination, whereby a lower E a corresponds to an easier delamination.

Impact of Linewidth on Backend Dielectric TDDB and Incorporation of the Linewidth Effect in Full Chip Lifetime Analysis

“…15), from which we determine the Weibull parameters (η, β) (Figs. [16][17][18]. This (η, β) corresponds to a test structure associated with the vulnerable length, spacing pair (L, S D ), which is area scaled with (3) to find the dielectric segment Weibull parameters.…”

“…It is likely that failures in the upper percentile range are due to breakdown paths through the bulk dielectric, while failures in the lower percentiles may be due to the development of traps at the top passivating dielectric layer interface, where lattice mismatch creates a large number of dangling bonds. Early failures have also been traced to delamination at the capping layer interface [17]. This bimodal failure rate distribution also indicates that the failure paths are associated with different defect generation rates.…”

Effect of Ta migration from sidewall barrier on leakage current in Cu/SiOCH low-k dielectrics

“…Therefore, it is imperative to identify and understand the root causes that degrade the dielectric performance in terms of leakage current, breakdown strength, and time to failure. Failure mechanisms such as diffusion of Cu ions into the dielectric, 1-3 dielectric cracking, 4 delamination, 5 and intrinsic dielectric breakdown 6 have been reported. Low-k dielectric plasma damage at the sidewall ͑i.e., carbon depletion phenomena͒, 7 moisture adsorption, 8 chemical-mechanical polishing ͑CMP͒ slurry, and post-CMP cleaning solutions 9 as well as liner deposition process 10 were the few main causes identified.…”

Investigation of interconnect layout on CU/Low-K TDDB reliability

“…The shape is found to be similar; hence any field enhancement that occurs will be due to the proximity of the adjacent metal line, and not caused by the curvature of the cathodes and anodes. just under the capping layer [88]. The reason is attributed to the tapering of the metal wire.…”

“…Due to the difference in geometry and area between the small area and conventional test structures, more study should be done to understand how the data gathered from the small area test structures relate to the conventional structure. It was pointed out by Muraka [9] Tan's small area test structure also has the advantage of confining the breakdown path, making it convenient for physical failure analysis as it fits the size of a transmission electron microscope (TEM) sample, allowing the challenging fault localization procedures to be omitted [54,88]. Voltage ramp tests and TDDB stressing were done on these 2 structures.…”