Delay‐compensation block for first‐order low‐pass delta‐sigma modulators

Abstract

Implementing the Delta Sigma Modulator (DSM) processing blocks on hardware is challenging due to the additional tap delays required by the digital processing blocks to process and output the result. The tap‐delays, known as latency, are necessary for the Field Programmable Gate Array (FPGA) operation to allow the logic gates to process the data at a given clock rate. These latencies alter the transfer function of the first‐order DSM as they present additional tap‐delays to the inherent delays within the DSM loop. A compensation block for the first‐order DSM is proposed to cancel‐out the effect of these latencies. By studying the transfer function, a combination of delays able to reconstruct the correct transfer function is determined. The solution was implemented on FPGA and tested using a 2.5 MHz signal. The post‐compensated DSM achieved a Signal‐to‐Noise‐and‐Distortion Ratio (SNDR) = 42 dB and an Adjacent Channel Leakage Ratio (ACLR) = 39 dB.