Delay Efficient 32-bit Carry-Skip Adder

Abstract

The design of a 32-bit carry-skip adder to achieve minimum delay is presented in this paper. A fast carry look-ahead logic using group generate and group propagate functions is used to speed up the performance of multiple stages of ripple carry adders. The group generate and group propagate functions are generated in parallel with the carry generation for each block. The optimum block sizes are decided by considering the critical path into account. The new architecture delivers the sum and carry outputs in lesser unit delays than existing carry-skip adders. The adder is implemented in 0.25 μm CMOS technology at 3.3 V. The critical delay for the proposed adder is 3.4 nanoseconds. The simulation results show that the proposed adder is 18% faster than the current fastest carry-skip adder.

New energy‐efficient hybrid wide‐operand adder architecture

“…However, the high delay of the RCA structure makes it inefficient for modern applications. Other structures like the carry select (CSL) [9][10][11], carry skip (CSK) [12][13][14][15], and carry-look ahead (CLA) adders [16][17][18] are faster than RCAs at the expense of increased area and power consumption. Moreover, parallel prefix (PPF) adders are fast structures composed of three main components: (i) the preparation unit that produces generate and propagate signals; (ii) the carry network that creates and propagates carry bits; and (iii) the last component that computes the value of the sum based on the bitwise XORing of the carry bits (the output of ii), and the two input bits.…”