Delay fault modelling/simulation using VHDL-AMS in multi-Vdd systems

Abstract

Abstract-With the growing density of Very Large Scale Integrated(VLSI) circuits, traditional digital fault simulation is no longer a viable option. This is because of analogue-like behaviour in digital circuits. The need for fast fault simulation is one of the main requirements in test pattern generation. The trade off between accurate simulations at transistor level, as in SPICE and fast simulation at gate level using a Hardware Descriptive Language (HDL) can be achieved by using behavioural modelling languages such as VHDL-AMS. In this paper, we have demonstrated that behavioural fault simulation for resistive faults can produce fast and accurate results.

Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review

“…The time-domain algorithm for fault simulation work in two iterative shells. One is the outer iteration that steps through [22] Fault modeling and simulation [23] Parametric fault simulation 2011 [24] Efficient time-domain simulation [25] Fault equivalence 2011 [26] Fault sensitivity analysis [27] Parametric variation 2011 [28] Fault sensitivity analysis [29] Behavioral level simulation 2012 [30] Fast fault simulation [31] Behavioral level simulation 2012 [32] Layout level defect injection [33] Fault sensitivity analysis 2012 [34] Inductive Fault analysis [35] High-level fault simulation 2013 [36] Numerical-based method [37] Parallel fault simulation 2013 [38] Inductive fault analysis [39] Tool for fault simulation 2013 [40] High-level fault simulation [9] Behavioral level simulation 2014 [41] Fault list compression technique [42] Multi-level hierarchical analogue fault simulation 2014 [43] Practical random sampling [44] Fast fault simulation for nonlinear analog circuits 2014 [45] Impedance calculation [46] [77] Macro modeling of analog components [78] Behavioral level fault simulation 2018 [79] Simulation at high abstraction level [80] Systematic method 2018 [81] Random sampling [82] Mixed-mode fault simulation 2019 [2] Likelihood-weighted random sampling of defects [83] Test point selection 2019 [84] Industrial Analog fault simulator [85] Analog fault injection and simulation interface 2019 ...…”

“…These techniques are possibly best if used in multi-level fault simulations. The idea of modeling faults at the behavioral level has been discussed in [9], [29], [31], [35], [53], [62], [66], [74], [78], [82], [89], [91] to speed up the fault simulation process.…”

“…Fault simulation using high-level models [9], [53], [91], [29], [62], [89], [82], [35], [31], [58], [66], [74], [78], [40], [87], [55], [42], [82], [91], [56] Fault simulation using fault grouping [70], [21], [48], [46], [54], [92], [65], [41], [86], [8], [25], [60] Concurrent and parallel fault simulation [7], [51], [69], [61], [37], [51], [30] Fault sensitivity analysis [11], [75], [33], [49], [26], [28] Monte Carlo simulation [10], [47], [22] DC fault simulation [64]…”