Delay Fault Testing for VLSI Circuits

Abstract

Unlike stuck-at fault testing, delay testing is closely tied to the test application strategy. This means that before tests for delay faults are derived it is necessary to know how these tests will be applied to the circuit. The testing strategy depends on the type of the circuit (combinational, scan, non-scan or partial scan sequential) as well as on the speed of the testing equipment. Ordinarily, testing delay defects requires that the test vectors be applied to the circuit at its intended operating speed. However, since high speed testers require huge investments, testers currently used in test facilities could be slower than the new designs that need to be tested on them. Testing high speed designs on slower testers requires special test application and test generation strategies.The focus of this chapter is on different test application schemes for combinational and sequential circuits. Techniques used for testing scan as well as non-scan designs are described. Also, the issue of testing high speed designs using slow testers is addressed and some of the currently available solutions to this problem are described.

Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA

“…Thus, we can conclude that, by using the proposed method, we can measure path delays of all global routing resources in a comparable time to stuck-at fault testing for global routing resources. While stuck-at fault testing detects only stuck-at faults, delay fault testing detects delay faults as well as stuck-at faults [17]. Since the proposed testing targets delay faults, we can conclude that the proposed testing detects more faults with a comparable time to traditional stuck-at fault testing.…”

Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion

“…From this reason, a path through the fault should be sensitized for testing the transition delay fault. In path delay fault testing, a signal is an on-input of path p if it is on path p. If a gate g is on path p and an input line of the gate g is not on p, the line is called an off-input of p [1], [17]. A logic value is the controlling value to a gate if it determines the output value of the gate regardless of the values on the other inputs to the gate.…”

“…With the increasing speed of integrated circuits, violations of the performance specifications are becoming a major factor affecting the product-quality level [1]. Delay defects that degrade performance and cause timing related failures are emerging as a major problem in nanometer technologies.…”

Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques

“…Robust test patterns are harder to obtain than non-robust test patterns. For more details about sensitization criteria, we refer to [13].…”