Delay Optimized Redundant Binary Adders

Jose, Babita R.; Radhakrishnan, D.

doi:10.1109/icecs.2006.379838

Cited by 8 publications

(3 citation statements)

References 9 publications

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“…The Dadda 4:2 and Counter 7:3 trees use the same reduction strategy with the Dadda tree using though 4:2 and 7:3 compressors, respectively. In the Redundant binary tree, the partial products are in a redundant representation and the addition is performed by redundant binary adders [23] in the form of a binary tree. A Carry Look-Ahead adder is used as the final adder in all multipliers.…”

Section: Exploring the Efficiency Of Partial Product Perforationmentioning

confidence: 99%

Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation

Zervakis

Tsoumanis

Xydis

et al. 2016

IEEE Trans. VLSI Syst.

117

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Approximate computing has received significant attention as a promising strategy to decrease power consumption of inherently error tolerant applications. In this paper, we focus on hardware level approximation by introducing the Partial Product Perforation technique for designing approximate multiplication circuits. We prove in a mathematically rigorous manner that in partial product perforation the imposed errors are bounded and predictable, depending only on the input distribution. Through extensive experimental evaluation, we apply the partial product perforation method on different multiplier architectures and expose the optimal architecture-perforation configuration pairs for different error constraints. We show that, compared with the respective exact design, the partial product perforation delivers reductions of up to 50% in power consumption, 45% in area and 35% in critical delay. Also, the product perforation method is compared with state-of-the-art approximation techniques, i.e. truncation, Voltage Over-Scaling and logic approximation, showing that it outperforms them in terms of power dissipation and error.

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Section: Exploring the Efficiency Of Partial Product Perforationmentioning

confidence: 99%

Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation

Zervakis

Tsoumanis

Xydis

et al. 2016

IEEE Trans. VLSI Syst.

117

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“…2. Fast RBAs defined in Jose et al [11] can be used for RB addition using the alternate Encoding 2 in Table I. Our design could also eliminate the error-correction block used in the partial product accumulator [10]. This will enable us to expand the number of bits in the multiplier to 64 bits, while keeping the number of adder stages to four.…”

Section: Partial Product Accumulationmentioning

confidence: 99%

Fast redundant binary partial product generators for booth multiplication

Jose

Radhakrishnan

2007

2007 50th Midwest Symposium on Circuits and Systems

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The use of signed-digit number systems in arithmetic circuits has the advantage of constant time addition irrespective of word length. In this paper, we present the design of a binary signed-digit partial product generator, which expresses each normal binary operand in one's complement form with an extra bit denoting the sign bit of the operand. The carry free nature of RBAs is exploited to add the extra bits with the partial products, without using additional adder stages. This technique allows RB encoding to be used in multipliers with operand widths which are perfect powers of two, without increasing the delay of partial product accumulation. The proposed partial product generator achieves the highest reduction in the number of partial products for a radix-4 multiplier (78%), by combining advantages of RB encoding with RB addition. The proposed partial product generator together with a set of fast redundant binary adder stages configured in a binary tree fashion can result in the design of high performance multipliers.

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“…The Dadda 4:2 and Counter 7:3 trees use the same reduction strategy with the Dadda tree using though 4:2 and 7:3 compressors, respectively. In the Redundant binary tree, the partial products are in a redundant representation and the addition is performed by redundant binary adders [107] in the form of a binary tree. A Carry Look-Ahead adder is used as the final adder in all multipliers.…”

Section: Exploring the Efficiency Of Partial Product Perforationmentioning

confidence: 99%

Design automation and synthesis techniques for approximate computing

Zervakis¹,

Ζερβάκης²

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Οι τεχνολογίες πληροφορικής βρίσκονται πλέον σε μια εποχή που για να διατηρηθεί αλλά και να βελτιωθεί η απόδοση και αποτελεσματικότητα των υπολογιστικών συστημάτων είναι αναγκαίες ριζικές αλλαγές συγκριτικά με τις παραδοσιακές τεχνικές. Ο προσεγγιστικός υπολογισμός αποτελεί ένα χαρακτηριστικό πρότυπο ριζικής μεταβολής που έχει εισέλθει στο σχεδιασμό και τη λειτουργία των σύγχρονων συστημάτων. Η διατριβή αυτή επικεντρώνεται στην μελέτη και σχεδίαση προσεγγιστικών επιταχυντών υλικού. Οι υπάρχουσες μεθοδολογίες σχεδίασης προσεγγιστικών κυκλωμάτων εφαρμόζουν κατά κύριο λόγο μονο-επίπεδες προσεγγιστικές τεχνικές, περιορίζοντας έτσι σημαντικά τα ενεργειακά οφέλη από την εφαρμογή του προσεγγιστικού υπολογισμού. Ο στόχος αυτής της διατριβής είναι να μεγιστοποιήσει τα ενεργειακά οφέλη των προσεγγιστικών κυκλωμάτων και να προτείνει συστηματικές μεθοδολογίες για την εφαρμογή του προσεγγιστικού υπολογισμού, έτσι ώστε να επιτρέψει την αξιοποίησή του στον τομέα της σχεδίασης ψηφιακών συστημάτων. Για να μεγιστοποιήσουμε την απόδοση των προσεγγιστικών κυκλωμάτων μελετάμε, προτείνουμε, και καταστούμε δυνατή την εφαρμογή πολυ-επίπεδων προσεγγιστικών τεχνικών για την παραγωγή τόσο προσεγγιστικών αριθμητικών κυ- κλωμάτων όσο και επιταχυντών υλικού. Τα ανωτέρω επιτυγχάνονται μέσα από τα τέσσερα αυτοματοποιημένα πλαίσια σχεδίασης και σύνθεσης που προτείνουμε: VOSsim, Partial Product Perforation, HAM, και METHADONE. Τα πλαίσια αυτά αξιολογήθηκαν διεξοδικά μέσω εκτενούς πειραματικής διαδικασίας και συγκρίθηκαν με τις εκάστοτε βέλτιστες υπάρχουσες μεθοδολογίες και τεχνικές αποδεικνύοντας την αποδοτικότητά τους.

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Delay Optimized Redundant Binary Adders

Cited by 8 publications

References 9 publications

Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation

Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation

Fast redundant binary partial product generators for booth multiplication

Design automation and synthesis techniques for approximate computing

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