Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations

Abstract

The semiconductor industry has moved to FinFETs because of their superior ability to mitigate short-channel effects relative to CMOS. Thus, good FinFET delay and power models are urgently needed to facilitate FinFET IC design at the upcoming technology nodes. Another urgent problem that needs to be addressed with continued technology scaling is how to analyze circuit performance and power consumption under process, voltage, and temperature (PVT) variations. Such variations arise due to limitations of lithography that lead to variations in the physical dimensions of the device or due to environmental variations. In this article, we propose a delay/power modeling framework for analysis of FinFET logic circuits under PVT variations. We present models for FinFET logic gates and three FinFET SRAM cells. We use GenFin, which is a genetic algorithm based statistical circuit-level delay/power optimizer, to produce the models for functional units (FUs) employed in a processor. We compare the impact of PVT variations at the 22nm and 14nm FinFET technology nodes. We evaluate cache performance for various cache capacities and temperatures as well as that of FUs. Our device simulation results show that the 3σ/μ spread for 14nm circuits is, on average, 38.5% higher in dynamic power and 21.4% higher in logarithm of leakage power relative to 22nm FinFET circuits. However, the delay spread depends on the circuit.

System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation

“…This paper examines the case of FinFETs in particular. Tang et al 40 presented a detailed delay/power estimation of FinFET at the circuit level. They used statistical modelling to estimate the process variations impact on delay by comparing the process variation impact for the 22 43 They presented a model to estimate the performance of double-gate devices considering the impact of line-edge-roughness.…”

A novel optimization framework for controlling stabilization issue in design principle of FinFET based SRAM

“…Sakhare et al [14] have offered targeting mechanism for 10-nm FinFET SRAM by considering capacitance in order to establish technology high density SRAM bit cell. Tang et al [15] have presented a model based on Taylor expansion and genetic algorithm for examine the FinFET circuit devices under various parameters variations such as power, voltage and temperature. Asenov et al [16] have applied co-optimization tool to 22 nm FinFET based CMOS technology to demonstrate the FinFET to demonstrate the sensitivity of the FinFET to the fin-shaped changes induced by the process.…”