Delay testing of MOS transistor with gate oxide short

Gate-Oxide-Short Defect Analysis and Fault Modeling Based on FinFET's 3D Structure

“…Gate-Oxide-Short (GOS) is one of the dominant defects [6] that is complex to analyze and model, especially in FinFETs, due to its nonlinear impact on the transistor characteristics.…”

“…Moreover, random dopant fluctuations in FinFETs are lower due to undoped or lightly doped fins [6]. FinFETs provide higher drain currents at lower supply voltages; hence, making better performance with lower power consumption achievable.…”

“…GOS is a dominant defect [6], because of the continuous reduction in the transistor's critical dimensions and its dielectric thickness. This defect is also complex and hard to analyze since it modifies the transistor characteristics in different manners depending on its size and location [6]. Therefore, it is important to develop accurate defect models that can be used in obtaining reliable fault models and practical test patterns.…”

“…One side of the array represents the source, the other side of the array represents the drain and all transistor gates are connected to form a common gate terminal. The pinhole is modeled as a resistor, R GOS , that is connected between the common gate and one of the internal nodes of the bidimensional array [61], [6], as shown in Assuming all transistors in the array to be minimum-sized, the equivalent transistor that the defect is applied to, Figure 3.2(b), has larger effective width and length. Therefore, the split model cannot accurately represent a minimum-size defective transistor [61].…”

Electrical analysis of a domino logic cell with GOS faults

“…A detailed analysis of the behavior of a full CMOS logic gate affected by a GOS and possible detection have recently been proposed [11,12]. Nevertheless, the results obtained in case of a full CMOS logic gate cannot be transferred to Domino logic.…”