Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits

Abstract

Abstract-Partially depleted silicon-on-insulator (PD-SOI) technology has garnered more attention recently with regards to replacing traditional bulk-silicon technology as the mainstream technology of choice for high-performance/low-power digital applications. The increase in performance is due to the buried oxide layer, which provides a dramatic decrease in the source and drain junction capacitance, as well as a reduction in the traditional back biasing resulting from the body effect. The reported performance increases have been between 20% and 35%. However, this increase in performance comes at a cost of complexity from a performance measurement and delay testing perspective. Where the SOI transistor is faster than the bulk transistor, there exists a variation in delay caused by threshold voltage shifts that must be accounted for during manufacturing test. This paper explores these issues and proposes new test techniques for this promising technology.Index Terms-Delay testing, flip-flop design, silicon-on-insulator (SOI) testing.

Statistical timing and leakage power analysis of PD-SOI digital circuits

“…The history effect causes the variation of the V th in a PD-SOI device; this determines its propagation delay. The delay of PD-SOI can vary depending on initial conditions, switching history, slew rate, pulse width, and frequency of data [5][6][7]. Figure 2 shows the different variations of the propagation delay based on previous states of a device.…”

“…Therefore, traditional timing analysis tools must be enhanced to include the unique characterization of PD-SOI. Several papers have been published on new timing analysis tools for PD-SOI at logic and transistor levels [5][6][7]. However, these tools consider only the worst-case delay in PD-SOI digital circuits, or utilize the simple approach of a state-diagram model to ignore the uncertainty in the characteristics of PD-SOI.…”

“…Therefore, various methodologies have been proposed to reduce the static leakage power [8,9]. However, only a few methods have analyzed and modeled the leakage power in PD-SOI CMOS circuits; moreover, they do not fully consider the history effect on leakage power [7,8]. In PD-SOI CMOS circuits, the main leakage components are subthreshold current and gate leakage current.…”

Delay testing of PD-SOI circuits

“…The thin film structure of SOI results a better performance in subthreshold slope and transconductance [6]. Oxide isolation structure lowers the leakage current and buried oxide structure improves the radiation harness of SOI devices [1]. Compared to bulk devices, the circuits built by SOI devices have a higher speed performance.…”

“…Level-Sensitive Scan Design (LSSD) used in conventional bulk technology [5]. In [1] new scan elements was proposed to overcome delay testing in SOI circuit, their solution suffer from superfluous chip area that was added to circuit because of extra latches in scan elements. Also complexity of required signals for delay testing in their solution increases test time.…”