Delay-verifiability of combinational circuits based on primitive faults

Ke, Wuudiann; Menon, P.R.

doi:10.1109/iccd.1994.331861

Cited by 14 publications

(23 citation statements)

References 8 publications

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“…These groups of FS paths belong to the class of faults called primitive faults [78,79]. The primitive faults will be described in greater detail in Section 5.3.…”

Section: Functional Sensitizable Path Delay Faultsmentioning

confidence: 99%

Delay Fault Testing for VLSI Circuits

Krstić

Cheng

1998

Frontiers in Electronic Testing

256

120

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Unlike stuck-at fault testing, delay testing is closely tied to the test application strategy. This means that before tests for delay faults are derived it is necessary to know how these tests will be applied to the circuit. The testing strategy depends on the type of the circuit (combinational, scan, non-scan or partial scan sequential) as well as on the speed of the testing equipment. Ordinarily, testing delay defects requires that the test vectors be applied to the circuit at its intended operating speed. However, since high speed testers require huge investments, testers currently used in test facilities could be slower than the new designs that need to be tested on them. Testing high speed designs on slower testers requires special test application and test generation strategies.The focus of this chapter is on different test application schemes for combinational and sequential circuits. Techniques used for testing scan as well as non-scan designs are described. Also, the issue of testing high speed designs using slow testers is addressed and some of the currently available solutions to this problem are described.

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“…These groups of FS paths belong to the class of faults called primitive faults [78,79]. The primitive faults will be described in greater detail in Section 5.3.…”

Section: Functional Sensitizable Path Delay Faultsmentioning

confidence: 99%

Delay Fault Testing for VLSI Circuits

Krstić

Cheng

1998

Frontiers in Electronic Testing

256

120

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“…Such faults were defined in [9] for combinational circuits in terms of sensitizability of paths. We shall use a functional definition instead, so that it applies to both combinational and sequential circuits.…”

Section: Primitive Faults In Combinational Circuitsmentioning

confidence: 99%

“…Thus, an important problem in delay testing is to identify all faults that must be tested to guarantee that the tested circuit will function correctly at the tested speed and any lower speed. It has been shown that, for any combinational circuit, there exists a set of faults called primitive faults, that must be tested to guarantee correct timing [9,10]. The set of primitive faults may contain single and multiple path delay faults.…”

Section: Introductionmentioning

confidence: 99%

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On primitive fault test generation in non-scan sequential circuits

Tekumalla¹,

Menon²

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)

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“…None of the single paths contained in P M is strong non-robustly sensitized. The multi-path propagation mechanism for transition faults is analogous to that for multi-path delay faults [11].…”

Section: Weak and Strong Non-robust Fault Propagationmentioning

confidence: 99%

On generating high quality tests for transition faults

Shao

Pomeranz²,

Reddy³

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).

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In this work we propose a path-oriented test generation procedure called POTENT to generate high quality tests for transition faults. Both weak non-robust and strong non-robust tests can be generated by POTENT. We classify transition fault tests into six types according to their activation and propagation methods. The basic idea of POTENT is to test a transition fault along a longest testable path passing through the fault site. For transition faults that are activated or propagated through multipaths, heuristics are proposed to maximize the propagation delay of the target fault. We also propose an efficient method to evaluate the quality of a given transition fault test set. Experimental results show that POTENT generates higher quality transition fault test sets than the conventional test generation method.

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Delay-verifiability of combinational circuits based on primitive faults

Cited by 14 publications

References 8 publications

Delay Fault Testing for VLSI Circuits

Delay Fault Testing for VLSI Circuits

On primitive fault test generation in non-scan sequential circuits

On generating high quality tests for transition faults

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