Delayed consistency and its effects on the miss rate of parallel programs

Abstract

In cache based multiprocessors a protocol must maintain coherence among replicated copies of shared writable data. In delayed consistency protocols the effect of out-going and in-coming invalidations or updates are delayed. Delayed coherence can reduce processor blocking time as well as the effects of false sharing. In this paper, we introduce several implementations of delayed consistency for cache-based systems in the framework of a weaklyordered consistency model. A performance comparison of the delayed protocols with the corresponding On-the-Fly (non-del~ed) consistency protocol is made, through execution-driven simulations of four parallel algorithms. The results show that, for parallel programs in which false sharing is a problem, signljlcant reductions in the data miss rate of parallel programs can be obtained with just a small increase in the cost and complexity of the cache system.

Formal automatic verification of cache coherence in multiprocessors with relaxed memory models

“…The delayed protocol [10] is the target protocol to demonstrate the verification methodology proposed in this paper. The verification model includes features found in a wide spectrum of designs and is general enough to apply to other protocols under relaxed memory consistency models.…”

“…Owner [10], with the following meanings: A Keeper copy is loaded into the cache on a read miss, a block copy is Stale when a pending invalidation is in the IRB, and an Owner copy implies that the local copy has been modified. Because invalidations are not performed on-the-fly, an Owner copy does not necessarily mean an exclusive copy in the system but the Owner is responsible for providing the copy in response to other processors' misses.…”

“…A brief description of the protocol is outlined below for completeness. Detailed explanations of coherence messages and transactions can be found in [10] and in [26]. The following description is from the perspective of local cache C i .…”

“…Remember that a stale copy indicates a pending invalidation in the IRB. Actually we advocate implementing the IRB with a stale state in the cache [10]. Finally, the set of operations triggering state transitions in the global state machine are:…”

“…We also demonstrate the feasibility of verifying such cache protocols by applying a state based verification tool called SSM (for "Symbolic State Model") [25] to an aggressive cache protocol under relaxed memory models, called the delayed protocol [10]. The delayed protocol is an aggressive implementation of release consistency [14], in which the sending of invalidations and the effect of received invalidations are deliberately delayed until the next release and the next acquire respectively.…”