Essential Misses and Data Traffic in Coherence Protocols

Dubois, Michel; Skeppstedt, Jonas; Strenström, Per

doi:10.1006/jpdc.1995.1112

Cited by 16 publications

(9 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…• Word granularity: Tracking the read and writesets at the word granularity maintains the read-and write-sets exactly, i.e., no false sharing [29,28] occurs. However, this approach introduces higher overhead in terms of time and space (state information).…”

Section: Concurrency Controlmentioning

confidence: 99%

Transactional memory

Grahn¹

2010

Journal of Parallel and Distributed Computing

View full text Add to dashboard Cite

Current and future processor generations are based on multicore architectures where the performance increase comes from an increasing number of cores on a chip. In order to utilize the performance potential of multicore architectures the programs also need to be parallel, but writing parallel programs is a non-trivial task. Transactional memory tries to ease parallel program development by providing atomic and isolated execution of code sequences, enabling software composability and protected access to shared data. In addition, transactional memory has the ability to execute atomic code sequences in parallel as long as no data conflicts occur. Transactional memory implementation proposals exist for both hardware and software, as well as hybrid solutions. This special issue on transactional memory introduces transactional memory as a concept, presents an overview of some of the most important approaches so far, and finally, includes five articles that advances the state-of-the-art in transactional memory research.

show abstract

Section: Concurrency Controlmentioning

confidence: 99%

Transactional memory

Grahn¹

2010

Journal of Parallel and Distributed Computing

View full text Add to dashboard Cite

show abstract

“…Coherence misses are caused by producer-consumer sharing and by false sharing-sharing blocks that happen to cross boundaries between subgrids. 8 …”

Section: Performance Trade-offsmentioning

confidence: 99%

“…The result is that some updates are never needed and should be removed because they unnecessarily increase traffic. 8 One solution is to adopt a mechanism that invalidates the local copy when it has received a predefined number of updates with no intervening access by the local processor. Competitive updating is an example of such a protocol.…”

Section: Hybrid Update-invalidatementioning

confidence: 99%

Boosting the performance of shared memory multiprocessors

Stenström

Brorsson²,

Dahlgren³

et al. 1997

Computer

Self Cite

View full text Add to dashboard Cite

“…Many characterizations of program demands for data movement, like coherence miss ratio on global address space multiprocessors [4] or ratio of communication to computation [16] in message passing architectures, have been based on program averages. Characterizations of the distance between the data movement initiation and the use of the data have also been based on program averages, like the cache miss ratio used by [1] to model coarse grain multithreading and the prefetch distance used by [10] to model the effectiveness of prefetching techniques.…”

Section: Introductionmentioning

confidence: 99%