$\Delta \Sigma $ PLL Transmitter With a Loop-Bandwidth Calibration System

Akamine, Yukinori; Kawabe, Manabu; Hori, K.; Okazaki, T.; Kasahara, M.; Tanaka, Satoshi

doi:10.1109/jssc.2007.914325

Cited by 30 publications

(14 citation statements)

References 11 publications

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“…The proposed prototype achieves measured phase noise of -107.6 dBc/Hz@1 MHz from 5.23 GHz, but it only consumes power of 25.4 mW and chip area of 0.739 mm 2 . Although there have been some research attempts to overcome PVT variations such as in [16][17], and frequency characteristics [15] To minimize VCO gain variations on a single tuning curve such as in [18] …”

Section: Measured Resultsmentioning

confidence: 99%

“…The IEEE 802. 15.4a specification allows transferring this information with low-rate wireless personal area networks (LR-WPANs) [1].Therefore, enhancing the frequency synthesizer specs becomes very crucial. VCO plays an important role in the frequency synthesizer, therefore to improve phase noise and power dissipation of the VCO must be necessary.…”

Section: Introductionmentioning

confidence: 99%

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Analysis and implementation of a frequency synthesizer with low phase noise and wide tuning range for health care applications

Lai

Huang

Chen

et al. 2014

2014 7th International Conference on Biomedical Engineering and Informatics

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A frequency synthesizer with low phase noise, low chip area and low power dissipation operating at 5.2 GHz band is provide and processing 0.18-um CMOS from TSMC. The proposed design can be used for healthcare applications such as body sensor network. The proposed frequency synthesizer with a cross-coupled negative-resistance multiple-gated circuit (NRMGC) LC-tank voltage-controlled oscillator (VCO) which uses multiple-gate transistors achieves low phase noise. At the supply voltages of 0.9 V for analog circuits and1.8 V for digital circuits, the provide prototype achieves a wide frequency tuning range from 4.31 to 5.27 GHz relevant to 20.4%, a phase noise of -107.61 dBc/Hz at 1 MHz frequency offset from 5.23 GHz, a overall power consumption of 25.4 mW and a spectrum output power of -23.03 dBm. The chip area including pads only occupies 0.739 (0.825 × 0.896) mm 2 .

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Section: Measured Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analysis and implementation of a frequency synthesizer with low phase noise and wide tuning range for health care applications

Lai

Huang

Chen

et al. 2014

2014 7th International Conference on Biomedical Engineering and Informatics

View full text Add to dashboard Cite

show abstract

“…The averaging varactor technique is used to reduce the VCO gain variation caused by the varactor's nonlinearity [17]. The frequency characteristics are [18], although there have been some research attempts to overcome PVT variations such as in [19][20]. On a single tuning curve measured minimize VCO gain variations such as in [21] which limits the control voltage range.…”

Section: B Sample-hold-reset Loop Filter Circuitmentioning

confidence: 99%

Frequency synthesizer with filter to signal detection for health care wireless network applications

Lai

Huang

2014

Proceedings of 2nd International Conference on Information Technology and Electronic Commerce

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A 2.4 GHz integer-N frequency synthesizer is purposed in tsmc 0.18-μm CMOS process. The purposed design can be used for the IEEE 802.15.4a unlicensed ultra-wideband healthcare applications such as body sensor network to wireless connect with computer network. Electrocardiogram (ECG) is the important physiological parameters in human body. Through monitoring and analyzing ECG, the current-switching differential Colpitts VCO by charge pump linearization technique can know the health condition of human body and achieve the purpose of prevention and diagnosis for diseases accordingly. In this paper, a solution of this design with a discrete-time sample-hold-reset loop filter build in human body for monitoring ECG signal detection is purposed.

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“…3, consisting of a 2 nd -order MASH DSM [3], a 4-bit counter and a control logic block. When the data comes into the CDR, the BBPD will output "UP" and "Down" signals to the counter.…”

Section: B Calibration Pathmentioning

confidence: 99%

A 2.5Gb/s oversampling clock and data recovery circuit with frequency calibration technique

Yang

Lin³

2008

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems

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In this paper, a 2.5-Gb/s oversampling clock and data recovery (CDR) circuit with frequency calibration is realized for optical communication. The CDR circuit contains a fractional-N phase-locked loop (PLL), a delta-sigma modulator (DSM) and a data recovery circuit. The recovered clock is adjusted by the DSM for phase and frequency tuning, incorporating with the phase detector, when the incoming data rate changes. The CDR circuit is implemented with TSMC 0.18-um 1P6M CMOS technology. The simulation results show the proposed CDR circuit recovers the incoming data.

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$\Delta \Sigma $ PLL Transmitter With a Loop-Bandwidth Calibration System

Cited by 30 publications

References 11 publications

Analysis and implementation of a frequency synthesizer with low phase noise and wide tuning range for health care applications

Analysis and implementation of a frequency synthesizer with low phase noise and wide tuning range for health care applications

Frequency synthesizer with filter to signal detection for health care wireless network applications

A 2.5Gb/s oversampling clock and data recovery circuit with frequency calibration technique

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