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The Nasu Radio Interferometer, consisting of eight equally spaced, 20-m diameter fixed spherical antennas, was developed for the purpose of surveying unknown variable radio sources at 1.4 GHz. An asymmetrical Gregorian sub-reflector was designed and installed on each antenna for the purpose of correcting aberrations caused by the spherical reflector. The total collecting area is 2512 m 2 and the field-of-view of each antenna is 0. • 6 × 0. • 6. In survey observations a spatial-fast Fourier-transform (FFT)-type multi-beam system will be used. We report on the design of spherical reflectors and a digital back-end system, the basic principle of spatial-FFT image forming, and a result of interferometric observations with an FPGA-based digital correlator.

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Low noise and low power consumption are the most important features of radio frequency integrated circuits (RFICs) used in mobile phones. The offset-PLL transmitter architecture has been widely used for GSM applications because of its low-noise performance. Recently, a ∆Σ PLL transmitter has been studied because it can achieve equivalent noise performance with a lower power consumption compared to an offset-PLL transmitter [1,2]. A critical issue is to suppress the variation of loop bandwidth or loop gain setting of ∆Σ PLL due to process tolerances. In case of narrower loop bandwidth, phase error of the modulation signal is degraded because useful part of the spectrum is suppressed to some extent. On the other hand, in case of wider loop bandwidth, noise performance is degraded because of the increase in the phase noise and the quantization noise. To solve this issue, a new method for calibrating the loop gain is proposed. The proposed technique can automatically tune to ±2% accuracy of the loop gain. This accuracy is no more than 2 degrees-rms of the phase error of the GMSK modulated signal for GSM850, GSM900, DCS1800, and PCS1900 bands. The phase error has enough margin for GSM standard [3]. The calibration system uses double integration of the VCO output signal over the transient step response of the fractional-N divider. Figure 17.4.1. shows the block diagram of the proposed ∆Σ PLL transmitter. It consists of a fractional-N PLL block and a modulation block. The blocks in the dotted line are circuits for calibrating the PLL. The fractional-N PLL block is fabricated in a 0.25µm BiCMOS process, and an FPGA is used for the modulation block. The digital data is supplied to this transmitter in binary data format. A digital Gaussian filter is used to generate a GMSK modulated signal. A frequency channel selection value is added next, and the result fed to a 3 rd -order ∆Σ modulator. The ∆Σ modulator functions as a noise shaper, moving quantization noise to a higher frequency outside the channel bandwidth. This signal is applied to the divider in the fractional-N PLL block. As a result, the PLL is modulated, and the VCO output contains the GSM modulation spectrum.The transfer function T(s) of the closed loop PLL, from which the loop bandwidth is determined, can be written as:In this expression, "Kv", "H(s)" and "Icp" always appear together as a product. Thus, we can reduce the variation in T(s) by optimizing "Icp" only. The proposed calibration system is simple and achieves a short calibration time. It is based on the fact that the step response of a PLL depends on the loop gain. The calibration system measures the changes in the transient signal the VCO output frequency when a step signal is applied to the ∆Σ modulator. Figure 17.4.2 shows the waveforms at various points of the calibration circuit; the step input of the ∆Σ modulator is shown in (a), and the VCO output frequency is shown in (b). The result after integrating the VCO output frequency by a 16b ECL counter is as shown in (c). Further integration is done ...