Demonstrating distribution of SILC values at individual leakage spots

Abstract

Stress induced leakage current (SILC) in the order of 10 -17 to 10 -13 A were statistically evaluated by using an advanced test circuit. In this paper, the distribution of SILC was evaluated by changing measurement electric fields, electric stress intensities, device area, and oxide thickness. The distribution of SILC is determined by the current values at individual leakage spots when the device area is sufficiently small. When the electric stress intensity and the measurement field are small, the distribution of logarithm of SILC follows the Gumbel distribution because the maximum current values of the leakage spots determine the gate leakage current in small area MOSFETs. We also evaluated the time-dependent characteristics of SILC in small area MOSFETs. The random telegraph signals of gate leakage current were observed which also indicates the current values of individual leakage spots.

Experimental investigation of localized stress-induced leakage current distribution in gate dielectrics using array test circuit

“…Basically, RTS is caused by one or a few traps, and RTS is often observed in SILC. 24) These indicate that SILC has a strong relationship with the density of electron traps. It is considered that SILC is caused by the traps or is generated in a very small area that can be strongly influenced by electrons.…”

“…25) The measurements were carried out at −30 °C in order to accurately measure the gate current down to 10 −17 A. [21][22][23][24] The measured samples were fabricated using 0.…”

“…In previous studies, a statistical measurement system using an array test circuit was reported. [21][22][23][24] Figure 1 shows the diagram of the array test circuit. Horizontal and vertical shift registers are set to scan the output voltage of the source followers of a sample array, so that a large number of samples are measured rapidly.…”

“…Furthermore, the measurement temperature is −30 °C in order to reduce the junction leakage current from the peripheral circuit. With this measurement system, a SILC of more than 80,000 nMOSFETs with an accuracy on the 10 −17 A current order can be measured within 80 s. [21][22][23][24] In a previous study, the statistical measurement and analysis of localized SILC using an array test circuit were reported. However, the measurements were carried out only for a sample of 1 × 1 µm 2 gate area.…”

“…However, the measurements were carried out only for a sample of 1 × 1 µm 2 gate area. 24) In SSDM 2017, localized SILCs of nMOSFETs with various gate areas (1 × 1, 0.5 × 0.5, and 0.25 × 0.25 µm 2 ) were statistically measured and investigated. It was found that the localized SILC distribution follows the SILC defect density considering the Poisson distribution.…”