Demonstrating individual leakage path from random telegraph signal of stress induced leakage current

Teramoto, Akinobu; Inatsuka, T.; Tatsunori, Obara; Akagawa, Naoya; Kuroda, Rihito; Sugawa, Shigetoshi; Ohmi, Tadahiro

doi:10.1109/irps.2014.6861144

Cited by 1 publication

(1 citation statement)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It is considered that SILC is caused by the traps or is generated in a very small area that can be strongly influenced by electrons. 24,26,27) Figures 4(a)-4(c) show the Gumbel plots of the absolute values of SILC of nMOSFETs with the three gate areas after applying the stress of 9.5 MV=cm for 1,000 s with three E OX-Measure values of 6.1, 6.8, and 8.0 MV=cm. In Fig.…”

Section: Resultsmentioning

confidence: 99%

Experimental investigation of localized stress-induced leakage current distribution in gate dielectrics using array test circuit

Park

Teramoto

Kuroda

et al. 2018

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

Localized stress-induced leakage current (SILC) has become a major problem in the reliability of flash memories. To reduce it, clarifying the SILC mechanism is important, and statistical measurement and analysis have to be carried out. In this study, we applied an array test circuit that can measure the SILC distribution of more than 80,000 nMOSFETs with various gate areas at a high speed (within 80 s) and a high accuracy (on the 10 %17 A current order). The results clarified that the distributions of localized SILC in different gate areas follow a universal distribution assuming the same SILC defect density distribution per unit area, and the current of localized SILC defects does not scale down with the gate area. Moreover, the distribution of SILC defect density and its dependence on the oxide field for measurement (E OX-Measure ) were experimentally determined for fabricated devices.

show abstract

Section: Resultsmentioning

confidence: 99%