Demonstration of Complementary Ternary Graphene Field-Effect Transistors

Abstract

Strong demand for power reduction in state-of-the-art semiconductor devices calls for novel devices and architectures. Since ternary logic architecture can perform the same function as binary logic architecture with a much lower device density and higher information density, a switch device suitable for the ternary logic has been pursued for several decades. However, a single device that satisfies all the requirements for ternary logic architecture has not been demonstrated. We demonstrated a ternary graphene field-effect transistor (TGFET), showing three discrete current states in one device. The ternary function was achieved by introducing a metal strip to the middle of graphene channel, which created an N-P-N or P-N-P doping pattern depending on the work function of the metal. In addition, a standard ternary inverter working at room temperature has been achieved by modulating the work function of the metal in a graphene channel. The feasibility of a ternary inverter indicates that a general ternary logic architecture can be realized using complementary TGFETs. This breakthrough will provide a key stepping-stone for an extreme-low-power computing technology.

Reconfigurable Multivalue Logic Functions of a Silicon Ellipsoidal Quantum-Dot Transistor Operating at Room Temperature

“…For instance, negative-differential conductance (NDC) devices and negative-differential transconductance (NDT) transistors, which comprise diverse kinds of materials ( e.g. , biomolecule complexes, − organic materials, − carbon nanotubes, graphene, , van der Waals heterostructures, − oxide composites, , silicon (Si) nanostructures, − etc . ), are typical examples that can realize the MVL computing system beyond modern binary digital technology.…”

Investigation on Tunneling-based Ternary CMOS with Ferroelectric-Gate Field Effect Transistor Using TCAD Simulation

“…In the TCMOS, the off-current (I OFF ) levels of NMOS (n-type MOS) and PMOS (p-type MOS), which are generated by band-to-band tunneling (BTBT), should be matched to form the third V out state during inverter operations. In contrast to conventional ternary devices that utilize multithreshold voltage (Multi-V t ) transistors [6][7][8][9][10][11][12], the TCMOS can perform ternary operations using a pair of NMOS/PMOS with a single voltage (V t ); the fabrication process is also comparable to the conventional CMOS process, because it can be fabricated only by introducing one additional doping process. However, the TCMOS has the disadvantage of slow switching speed caused by low on-state current (I ON ).…”

Ternary Full Adder Using Multi-Threshold Voltage Graphene Barristors

“…he demand for more functionality at lower power consumption has been driving the limit of complementary metal-oxide-semiconductor (CMOS) technology [1]. Multi-valued logic (MVL) has been pursued for several decades because it can provide significant advantages to reduce the complexity of interconnects and the arithmetic operations [2]- [11]. Various types of single or composite devices exhibiting multiple states have been investigated for this purpose.…”

“…Shim et al demonstrated a ternary inverter using the graphene/WSe2 heterojunction, which showed light-induced negative differential transconductance (NDR) characteristics [10]. Kim et al demonstrated a complementary ternary logic device using graphene FET with npn and pnp channel profiles [11]. These devices showed the feasibility of the ternary logic device function with a low thermal budget integration process; however, their performances are not competitive to silicon devices yet.…”

“…where QM, QGraphene, and QS are the gate contact metal charge, the graphene layer charge of quantum capacitance containing the Dirac voltage shift (| V Dirac |=(1/απ)( E d /ħν F ) 2 ), and the semiconductor charge, respectively [11], [22]. The solid lines in Fig.…”